The following are sample pre-layout ASIC results (as reported by the synthesis tool and silicon vendor design kit) under typical process and operating conditions, with all core I/Os assumed to be routed on-chip, logical area excluding memory, and with equivalent gates count calculation using the smallest NAND2 gate available in the technology.
ASIC Technology |
Fmax (MHz) |
Logic Area (um2) |
Number of eq. gates |
Memory |
| TSMC 0.18µ process |
300 | ~244K | 25K |
6,912 |
| TSMC 0.09µ process | 500 | ~59K | 21K | 6,912 |