- Conforms to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T81 recommendation).
- Standalone operation.
- Pixel samples input.
- Standalone ISO/IEC 10918-1 JPEG stream output.
- Easily programmable through standard JPEG markers stream.
- Programmable image dimensions.
- Full range sample precision support (2 to 16 bits per sample)
- Up to four stream programmable Huffman tables.
- Programmable Restart Interval.
- Programmable Point Transform function.
- Programmable APPn and COM markers.
- Programming errors catch-up features.
- Compact, high-performance architecture.
- 21K gates achieving 500 MSamples/sec (0.09µ ASIC) under typical process and operating conditions.
- Also fits inexpensive FPGAs (see FPGA version datasheets)
- Robust and simple to use
- General purpose, fully stallable, streaming I/O interfaces.
Limitations with respect to the ISO/IEC 10918-1 standard:
- Up to three image-components are supported (Nf field of the SOF3 marker segment = 1 or 2 or 3).
- Single scan encoding (only one SOS marker segment, with Ns field = Nf).
- No DNL marker insertion (Y field of the SOF3 marker segment > 0).
- Fixed parameters.
- No sub-sampling (Hi and Vi fields of the SOF3 marker segment = 1).
- Prediction function is fixed to the left-hand predictor, predictor 1. (Ss field of SOS marker segment = 1).
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AHB Compression Core Bus Bridge
Related Products
- JPEGLS-E JPEG-LS Compression Encoder
- LJPEG-D Lossless JPEG Compression Decoder
- CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the LJPEG-E core
Related Information
Validated for Precision™ FPGA Synthesis
News Releases
- 06/13/05, Creo Uses CAST IP Cores in Advanced Leaf Aptus Digital Camera Backs
- 01/31/05, CAST Introduces the First Lossless JPEG (LJPEG) IP Cores
Technology Info
See the JPEG entry at Wikipedia.
Customer Applications
Leaf Imaging Ltd (formerly offered by Kodak) uses this core for fast, full-fidelity photo capture in their high-end Leaf® Aptus digital camera backs for professional photographers.
Lossless JPEG IP Core LJPEG-E Lossless JPEG Compression Encoder Core
The LJPEG-E core implements the Lossless JPEG (LJPEG) compression in a compact, high-performance, stand-alone package ideal for applications where bit-by-bit accurate reproduction of an image is essential.
The LJPEG-E conforms to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T81 recommendation). Rather than the Discrete Cosine Transform (DCT) functions used for lossy JPEG compression - which can introduce round-off errors - the LJPEG-E employs a predictor function as described in the specification. It thus encodes and compresses images with no information loss, and requires a significantly smaller physical implementation.
Evaluation designs show that the core requires just 21K gates in an ASIC. Its heavily optimized architecture also enables very high performance, reaching 500 MSamples/sec on 0.09µ process (under typical process and operating conditions).
The LJPEG-E is a fully synchronous, strictly positive-edge design with no internal three-state buffers. Comprehensive documentation and a complete verification environment - including a bit-accurate model - help designers integrate and verify the core.
See representative implementation results (each in a new pop-up window):
Applications
The LJPEG-E provides a fast, economical solution whenever lossless image compression is essential, including applications such as:
- Medical, military, and space imaging.
- Professional, studio-quality cameras and editing suites.
- High-end film and photo scanners.
- Industrial machine vision systems.
Block Diagram
Support
The LJPEG-E core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The LJPEG-E core has been verified through extensive simulation using a large set of test vectors and reference results, and through rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- A bit-accurate model (BAM) including custom vector generation support, and a software library of the bit accurate model functions
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including test vectors, expected results, and verification engine
- Simulation script
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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