Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Embedded Processors
BA22 Real-Time Embedded
BA22 Deeply Embedded
BA21 Low Power

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform

 

GPUs & Peripherals
See Graphics &
  Peripherals Cores >

These video and image compression cores and subsystems help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Complement or replace system processors with GPUs and easily integrate memories, peripherals, and hardware networking stacks into SoCs.

NOR Flash Controllers
Serial/SPI NOR Flash
Parallel NOR Flash

Device Controllers
smart card reader

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

AMBA Infrastructure
AMBA Infrastructure Cores
AHB 32-bit DMA


Interconnect Peripherals

See Interconnect Cores >

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

DisplayPort
Transmitter
•  Receiver

Ethernet MAC
•  1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
Hardware RTP Stack for H.264

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

PCI Express
Family Overview
x1/x4
x8
application interface


Data Link Controllers

• SDLC & HDLC

These encryption cores make it easy to build security into a variety of systems.

DES
DES single
DES triple

  • Conforms to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T81 recommendation).
  • Standalone operation.
    • Pixel samples input.
    • Standalone ISO/IEC 10918-1 JPEG stream output.
  • Easily programmable through standard JPEG markers stream.
    • Programmable image dimensions.
    • Full range sample precision support (2 to 16 bits per sample)
    • Up to four stream programmable Huffman tables.
    • Programmable Restart Interval.
    • Programmable Point Transform function.
    • Programmable APPn and COM markers.
    • Programming errors catch-up features.
  • Compact, high-performance architecture.
    • 21K gates achieving 500 MSamples/sec (0.09µ ASIC) under typical process and operating conditions.
    • Also fits inexpensive FPGAs (see FPGA version datasheets)
  • Robust and simple to use
    • General purpose, fully stallable, streaming I/O interfaces.
Limitations with respect to the ISO/IEC 10918-1 standard:
  • Up to three image-components are supported (Nf field of the SOF3 marker segment = 1 or 2 or 3).
  • Single scan encoding (only one SOS marker segment, with Ns field = Nf).
  • No DNL marker insertion (Y field of the SOF3 marker segment > 0).
  • Fixed parameters.
    • No sub-sampling (Hi and Vi fields of the SOF3 marker segment = 1).
    • Prediction function is fixed to the left-hand predictor, predictor 1. (Ss field of SOS marker segment = 1).

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PDF Datasheets

ASIC
Altera, Xilinx

Options:

AHB Compression Core Bus Bridge

Related Products

Compare
Versions

  • JPEGLS-E JPEG-LS Compression Encoder
  • LJPEG-D Lossless JPEG Compression Decoder
  • CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the LJPEG-E core

Related Information

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis

 

News Releases

Articles

See the JPEG entry at Wikipedia.

Blog Posts

Customer Applications

Leaf Imaging Ltd (formerly offered by Kodak) uses this core for fast, full-fidelity photo capture in their high-end Leaf® Aptus digital camera backs for professional photographers.

Lossless JPEG IP Core LJPEG-E Lossless JPEG Compression Encoder Core

The LJPEG-E core implements the Lossless JPEG (LJPEG) compression in a compact, high-performance, stand-alone package ideal for applications where bit-by-bit accurate reproduction of an image is essential.

The LJPEG-E conforms to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T81 recommendation). Rather than the Discrete Cosine Transform (DCT) functions used for lossy JPEG compression - which can introduce round-off errors - the LJPEG-E employs a predictor function as described in the specification. It thus encodes and compresses images with no information loss, and requires a significantly smaller physical implementation.

Evaluation designs show that the core requires just 21K gates in an ASIC. Its heavily optimized architecture also enables very high performance, reaching 500 MSamples/sec on 0.09µ process (under typical process and operating conditions).

The LJPEG-E is a fully synchronous, strictly positive-edge design with no internal three-state buffers. Comprehensive documentation and a complete verification environment - including a bit-accurate model - help designers integrate and verify the core.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Applications

The LJPEG-E provides a fast, economical solution whenever lossless image compression is essential, including applications such as:

Block Diagram

LJPEG-E Block Diagram

Support

The LJPEG-E core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The LJPEG-E core has been verified through extensive simulation using a large set of test vectors and reference results, and through rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation: