CAST LJPEG-D Core — XILINX FPGA Results

Xilinx results using balanced area/speed constraints during synthesis and place and route, while assuming that all core I/Os are routed off-chip.

Xilinx Device Slices
 Fmax
(MHz)
 I/O BRAM Special Features
 ISE
Spartan-3
3S1000-5
 2,983 40 81 2 RAMB16 - 12.2
Spartan-6
6SLX9-3
 1,290 50 81 1 RAMB16
1 RAMB8		 - 12.2
Virtex-5
5VLX30-3
 1,483 100 81 2 RAMB18 - 12.2
Virtex-6
6VLX75T-3
 1,259 120 81 2 RAMB18 - 12.2

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