The following are sample pre-layout ASIC results (as reported by synthesis tool and silicon vendor design kit) under typical process and operating conditions, with all core I/Os assumed to be routed on-chip, logical area excluding memory, and with equivalent gates count calculation using the smallest NAND2 gate available in the technology.
ASIC Technology |
Fmax (MHz) |
Logic Area (um2) |
Number of |
Memory |
| TSMC 0.18µ process |
200 | ~387K | 39K |
1,664 |
| TSMC 0.09µ process | 500 | ~102Κ | 36K | 1,664 |