The following are sample Altera results using balanced area/speed constraints during synthesis and place and route, while assuming that all megafunction I/Os are routed off-chip.
| Altera Devices | Logic | Fmax (MHz) |
Special Features | Design Tools |
| Cyclone EP1C20-C6 |
5,931 LEs | 45 | 2 M4Ks | Quartus 7.1 |
| Cyclone II EP2C20-C6 |
5,176 LEs | 50 | 2 M4Ks | Quartus 7.1 |
| Cyclone III EP3C16-C6 |
5,114 LEs | 50 | 2 M9Ks | Quartus 7.1 |
| Stratix EP1S10-C5 |
5,931 LEs | 50 | 2 M4Ks | Quartus 7.1 |
| Stratix II EP2S15-C3 |
4,415 ALUTs | 75 | 2 M4Ks | Quartus 7.1 |
| Stratix III EP3SE50-C2 | 4,337 ALUTs | 95 | 2 M9Ks | Quartus 7.1 |