Lossless JPEG IP Core LJPEG-D Lossless JPEG Compression Decoder Core

The LJPEG-D core implements a Lossless JPEG (LJPEG) decoder in a compact, high-performance, stand-alone package ideal for applications where bit-by-bit accurate reproduction of an image is essential.

The LJPEG-D decodes images that conform to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T.81 recommendation). Rather than the Discrete Cosine Transform (DCT) functions used for lossy JPEG compression - which can introduce round-off errors - the lossless part of the standard employs a reversible predictor function. The LJPEG-D core can thus decode images with no information loss, and requires a smaller physical implementation than what necessary for lossy JPEG image decoding.

Evaluation designs show that the core requires just 36K gates in an ASIC and that it fits in a variety of low-cost FPGA devices. Its heavily optimized architecture also enables very high performance, reaching 500 MSamples/sec on 0.09µ process (under typical process and operating conditions).

The LJPEG-D is a fully synchronous, strictly positive-edge design with no internal three-state buffers. Comprehensive documentation and a complete verification environment - including a bit-accurate model - help designers integrate and verify the core.

See representative implementation results (each in a new pop-up window):

Applications

The LJPEG-D provides a fast, economical solution whenever lossless image compression is essential, including applications such as:

• Medical, military, and space imaging.
• Professional, studio-quality cameras and editing suites.
• High-end film and photo scanners.
• Industrial machine vision systems.

Block Diagram

Support

The LJPEG-D core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The LJPEG-D core has been verified through extensive simulation using a large set of test vectors and reference results.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• A bit-accurate model (BAM) including custom vector generation support, and a software library of the bit accurate model functions
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including test vectors, expected results, and verification engine
• Simulation scripts
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide