Sample pre-layout results reported from a synthesis toll and silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip, for maximum line of 1024 8-bit samples for 3-component images.
| ASIC Technology | Logic Eq. Gates | Frequency | Memory |
| UMC 0.18µ process | 58,137 | 360 MHz | 102,076 bits |
| TSMC 0.09µ process | 51,506 | 700 MHz | 102,076 bits |