Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Embedded Processors
BA22 Real-Time Embedded
BA22 Deeply Embedded
BA21 Low Power

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform

 

GPUs & Peripherals
See Graphics &
  Peripherals Cores >

These video and image compression cores and subsystems help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Complement or replace system processors with GPUs and easily integrate memories, peripherals, and hardware networking stacks into SoCs.

NOR Flash Controllers
Serial/SPI NOR Flash
Parallel NOR Flash

Device Controllers
smart card reader

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

AMBA Infrastructure
AMBA Infrastructure Cores
AHB 32-bit DMA


Interconnect Peripherals

See Interconnect Cores >

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

DisplayPort
Transmitter
•  Receiver

Ethernet MAC
•  1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
Hardware RTP Stack for H.264

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

PCI Express
Family Overview
x1/x4
x8
application interface


Data Link Controllers

• SDLC & HDLC

These encryption cores make it easy to build security into a variety of systems.

DES
DES single
DES triple

ISO/IEC 14495-1 JPEG-LS Compliance

  • Any image size from 8 x 8 up to 64k x 64k
  • Grayscale, 4:4:4, 4:2:2, 4:1:1 and 4:2:0 sub-sampling formats
  • 2 up to 16 bits per sample
  • Programmable point transform
  • Programmable local gradient thresholds and context parameters reset threshold value (up to 64)
  • Single scan encoding
  • Optional Near-Lossless mode

Smooth System Integration

  • Single clock per input sample encoding
  • Programmable through standard JPEG-LS marker segments
  • Automatic headers generation
  • Automatic program-once encode-many operation
  • Simple, microcontroller like, programming interface
  • Flow controllable, streaming-capable Avalon-ST™ I/O data interfaces

Easy Verification & Technology Mapping

  • Extensive documentation
  • Bit Accurate Model (BAM) and Test Vector generator
  • Self checking testbench environment
  • Sample scripts
  • Fully portable HDL source code
  • No internal tri-states
  • Scan-ready design
  • Strictly positive edge triggered design using D-type only Flip-Flops
  • Fully synchronous operation
  • No need for special timing constraints

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PDF Datasheets

ASIC
Microsemi, Altera, Xilinx

Options:

AHB Compression Core Bus Bridge

Related Products

Compare
Versions

  • LJPEG-D Lossless JPEG Compression Decoder
  • LJPEG-E Lossless JPEG Compression Encoder
  • CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the JPEGLS-E core

Related Information

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis

 

News Releases

Articles

LOCO-I home page.

JPEGLS page at jpeg.org.

Lossless JPEG at Wikipeda..

Blog Posts

JPEG Lossless IP Core JPEGLS-E JPEG-LS Compression Encoder Core

The JPEGLS-E core is a standalone and high-performance JPEGLS encoder for lossless still image and video compression applications. The core implements the ISO-14495-1/ITU-T.87 standard, which is based on the low complexity and highly efficient LOCO-I algorithm.

The JPEGLS-E delivers leading lossless compression efficiency on a highly efficient hardware architecture. A single instantiation of the core can encode 4K UHDTV or higher rates, and synthesizes to less than 60,000 gates. It is originally provided with FIFO-like pixel and stream input /output interfaces, but other standard interfaces (e.g. AMBA/AHB) are also available. Being carefully designed, rigorously verified, and production-proven, the JPEGLS-E is a reliable and easy-to-integrate core. Ease of integration is served by a complete verification environment, including a bit-accurate software model.

See representative implementation results (each in a new pop-up window):

ASIC numbers Microsemi numbers Altera numbers Xilinx numbers

Applications

The JPEGLS-E can be utilized in a variety of image and video lossless compression encoder applications including:

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. The core is silicon proven in FPGA technologies.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation: