ISO/IEC 14495-1 JPEG-LS Compliance
- Any image size from 8 x 8 up to 64k x 64k
- Grayscale, 4:4:4, 4:2:2, 4:1:1 and 4:2:0 sub-sampling formats
- 2 up to 16 bits per sample
- Programmable point transform
- Programmable local gradient thresholds and context parameters reset threshold value (up to 64)
- Single scan encoding
- Optional Near-Lossless mode
Smooth System Integration
- Single clock per input sample encoding
- Programmable through standard JPEG-LS marker segments
- Automatic headers generation
- Automatic program-once encode-many operation
- Simple, microcontroller like, programming interface
- Flow controllable, streaming-capable Avalon-ST™ I/O data interfaces
Easy Verification & Technology Mapping
- Extensive documentation
- Bit Accurate Model (BAM) and Test Vector generator
- Self checking testbench environment
- Sample scripts
- Fully portable HDL source code
- No internal tri-states
- Scan-ready design
- Strictly positive edge triggered design using D-type only Flip-Flops
- Fully synchronous operation
- No need for special timing constraints
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AHB Compression Core Bus Bridge
Related Products
- LJPEG-D Lossless JPEG Compression Decoder
- LJPEG-E Lossless JPEG Compression Encoder
- CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the JPEGLS-E core
Related Information
Validated for Precision™ FPGA Synthesis
News Releases
Technology Info
LOCO-I home page.
JPEGLS page at jpeg.org.
Lossless JPEG at Wikipeda..
JPEG Lossless IP Core JPEGLS-E JPEG-LS Compression Encoder Core
The JPEGLS-E core is a standalone and high-performance JPEGLS encoder for lossless still image and video compression applications. The core implements the ISO-14495-1/ITU-T.87 standard, which is based on the low complexity and highly efficient LOCO-I algorithm.
The JPEGLS-E delivers leading lossless compression efficiency on a highly efficient hardware architecture. A single instantiation of the core can encode 4K UHDTV or higher rates, and synthesizes to less than 60,000 gates. It is originally provided with FIFO-like pixel and stream input /output interfaces, but other standard interfaces (e.g. AMBA/AHB) are also available. Being carefully designed, rigorously verified, and production-proven, the JPEGLS-E is a reliable and easy-to-integrate core. Ease of integration is served by a complete verification environment, including a bit-accurate software model.See representative implementation results (each in a new pop-up window):
Applications
The JPEGLS-E can be utilized in a variety of image and video lossless compression encoder applications including:
- Medical, military and space imaging
- Professional, studio quality cameras and editing suites
- High-end film and photo scanners
- Industrial machine vision system
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements. The core is silicon proven in FPGA technologies.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench (Xilinx and Altera Verilog versions use Verilog 2001)
- Bit-Accurate Model
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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