Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

Processor Peripherals
AHB 32-bit DMA
AMBA Infrastructure Cores

Legacy Processors
See Legacy Cores >

These video and image compression cores help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Block/Raster Converters
block-to-raster
raster-to-block
raster-block bidirect

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Functions & Converters
Color Space Converter

Video Deinterlacers
Basic

Quickly complete the standrd parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores. Choose high-speed DisplayPort or PCI Express, Ethernet MACs, the CAN bus for automotive systems, and more.

High-Speed Serial
PCI Express
Family Overview
x1/x4
x8
application interface

Parallel
ECP slave
ATA/IDE interface

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

TCP/IP Stacks
UDP/IP stack

Ethernet MAC
Device Controllers

10/100
10/100 lite
Gigabit
Gigabit lite
Gigabit PCS

MAC Platforms
MAC/PCI

Customers find these cores to be an excellent solution for preserving existing product board designs when critical chips are no longer available for purchase.

 
80186XL
80186EC
80188EC
80251
387L math

DSPs
32025 16-bit
32025TX 16-bit

 

 

Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Cores for integrating security, controlling devices and displays, and other SoC functions.

Device Controllers
smart card reader

IR Remote Controls
RC5
NEC

Audio Interfaces
I2S-SC
I2S-MC
SPDIF

ISO/IEC 14495-1 JPEG-LS Compliance

  • Any image size from 8 x 8 up to 64k x 64k
  • Grayscale, 4:4:4, 4:2:2, 4:1:1 and 4:2:0 sub-sampling formats
  • 2 up to 16 bits per sample
  • Programmable point transform
  • Programmable local gradient thresholds and context parameters reset threshold value (up to 64)
  • Single scan encoding
  • Optional Near-Lossless mode

Smooth System Integration

  • Single clock per input sample encoding
  • Programmable through standard JPEG-LS marker segments
  • Automatic headers generation
  • Automatic program-once encode-many operation
  • Simple, microcontroller like, programming interface
  • Flow controllable, streaming-capable Avalon-ST™ I/O data interfaces

Easy Verification & Technology Mapping

  • Extensive documentation
  • Bit Accurate Model (BAM) and Test Vector generator
  • Self checking testbench environment
  • Sample scripts
  • Fully portable HDL source code
  • No internal tri-states
  • Scan-ready design
  • Strictly positive edge triggered design using D-type only Flip-Flops
  • Fully synchronous operation
  • No need for special timing constraints

Contact Sales
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+1 800.391.8300

PDF Datasheets

ASIC
Actel, Altera, Xilinx

Options:

AHB Compression Core Bus Bridge

Related Products

Compare
Versions

  • LJPEG-D Lossless JPEG Compression Decoder
  • LJPEG-E Lossless JPEG Compression Encoder
  • CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the JPEGLS-E core

Related Information

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis

 

News Releases

Technology Info

LOCO-I home page.

JPEGLS page at jpeg.org.

Lossless JPEG at Wikipeda..

JPEG Lossless IP Core JPEGLS-E JPEG-LS Compression Encoder Core

The JPEGLS-E core is a standalone and high-performance JPEGLS encoder for lossless still image and video compression applications. The core implements the ISO-14495-1/ITU-T.87 standard, which is based on the low complexity and highly efficient LOCO-I algorithm.

The JPEGLS-E delivers leading lossless compression efficiency on a highly efficient hardware architecture. A single instantiation of the core can encode 4K UHDTV or higher rates, and synthesizes to less than 60,000 gates. It is originally provided with FIFO-like pixel and stream input /output interfaces, but other standard interfaces (e.g. AMBA/AHB) are also available. Being carefully designed, rigorously verified, and production-proven, the JPEGLS-E is a reliable and easy-to-integrate core. Ease of integration is served by a complete verification environment, including a bit-accurate software model.

See representative implementation results (each in a new pop-up window):

ASIC numbers Actel numbers Altera numbers Xilinx numbers

Applications

The JPEGLS-E can be utilized in a variety of image and video lossless compression encoder applications including:

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. The core is silicon proven in FPGA technologies.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

 

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