Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

RTP Encapsulation For JPEG Streams

  • Compliant to RFC 2435
  • Enables control of RTP packet size
    • Run-time programmable maximum stream bytes per RTP packet
  • In-band Quantization Table support

Easier Integration For Faster Development

  • Processor-less, standalone operation
  • AMBA AXI Interfaces
    • AXI4-Lite Control/Status register interfaces
    • AXI4-Streaming interfaces for packet data
  • Altera Avalon Interfaces
    • Avalon-MM Control/Status register interfaces
    • Avalon-ST interfaces for packet data
  • Available pre-integrated with:
    • JPEG Encoder cores from CAST
    • UDP/IP Hardware Stack from CAST
    • Altera, Xilinx, or other third-party Ethernet MAC core

 

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

General Product Brief

Related Products

  • JPEG-E-S Baseline JPEG Encoder Core
  • JPEG-EX-S Baseline and Extended JPEG Encoder Core
  • JPEG-EX-F Ultra-Fast Baseline and Extended JPEG Encoder Core
  • UDPIP UDP/IP Hardware Protocol Stack Core

News Releases

Articles

See the JPEG entry at Wikipedia.

See the  Motion JPEG entry  at Wikipedia.

Blog Posts

JPEG2RTP Hardware RTP Stack for JPEG

Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates JPEG streams to RTP packets compliant with RFC 2435.

The JPEG2RTP can be directly connected to the output of a JPEG encoder to output RTP packets, which can subsequently be forwarded for UDP/IP or TCP/IP encapsulation. The hardware stack produces complete RTP packets, without the need for any host-processor assistance. Along with CAST’s UDP/IP hardware stack, the JPEG2RTP core is ideal for offloading the demanding task of RTP/UDP/IP encapsulation from a host processor, and enables JPEG video streaming even in processor-less SoC designs.

The core is easy to integrate in systems with or without a host processor. JPEG stream and RTP packet data are input/output via dedicated streaming-capable AMBA® AXI4®-Stream or Altera® Avalon®-ST interfaces, enabling direct connection to hardware video encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by AXI4-Lite or Avalon-MM interface.

The JPEG2RTP core is available in RTL source or as a targeted FPGA netlist. Platforms integrating the core along with JPEG encoder, UDP/IP, and eMAC cores, are available from CAST, and can enable rapid development of video over IP systems.

Applications

The JPEG2RTP core is suitable for a wide variety systems and devices featuring JPEG video streaming over IP networks. A sample block diagram of such systems is provided below.

Block Diagram

JPEG2RTP Hardware RTP Stack for JPEG Block Diagram

Support

The JPEG2RTP as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

 

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