- JPEG 2000 compliance
- Both lossless and lossy compression
- Error-resilient compression
- Rate control
- Headers syntax processing (JPC, JP2, proprietary)
- Real JPEG2000 Performance
- No hardware simplification compromises
- Not based on bypass and parallel mode of entropy coding
- High-quality, accurate rate-control
- Region Of Interest
- Flexible Input Image Format
- All widely used sub-sampling formats (e.g. 444, 422, etc)
- Image up to 65,535x65,535
- Tile size up to 8,192x8,192
- Up to 4 color components
- 8 up to 16 bits per sample
- Programmable JPEG 2000 options
- 2D-DWT filter type (5/3 or 9/7)
- Number of 2D-DWT levels
- Quantization tables
- Entropy-coding switches (reset, restart, segmark)
- Input format (pixel depth, image and tile size, number of components, sub-sampling factors)
- Code-block size (64 or 32 or 16 on each dimension)
- Up to 30 quality layers
- Compression ratio per quality layer
- Tunable architecture during synthesis
- Configurable number of entropy coding units
- Configurable maximum image/tile size
- Flexible Interfaces
- 16-bit synchronous SRAM-style host interface
- Dedicated pixel-in and stream-out interfaces
- Independent of external memory type (DDR2/3. SDRAM, SRAM, etc.)
- Glue-less connection to Xilinx, Altera and CAST memory controllers
Call or click.
- JPEG2000-AP JPEG2000 Encoding Application Platform
- DDR/DDR2 SDRAM Memory Controller IP core
- AES encryption IP cores
- CCBB-AHB AHB Compression Core Bus Bridge
- PCI and PCI Express IP cores
- 06/04/07, CAST JPEG 2000 Encoder Core now Faster and More Capable
- 06/10/02, CAST JPEG 2000 Encoder Core Provides Fast, Flexible Image Compression
Papers & Articles
CAST/Avnet DesignCon paper: A
New Reference Design Development Environment for JPEG 2000
News and Info on the JPEG 2000 standard
An Evaluation of Motion JPEG 2000 for Video Archiving (PDF)
Try it Yourself
Evaluate this core in hardware with the complete, ready-to-run, JPEG 2000 Application Platform package.
See the JPEG 2000 entry at Wikipedia.
JPEG 2000 IP Core JPEG2K-E JPEG 2000 Compression Encoder Core
The JPEG2K-E core is a complete high performance JPEG2000 - ISO/IEC 15444-1 image compression solution targeted for video and high bandwidth image compression applications.
The JPEG2k-E core delivers real JPEG2000 compression efficiency. Commonly used hardware simplification compromises, such us bypass and parallel mode of the entropy coding process, that damage the JPEG2000 rate-distortion efficiency have not been adopted. Furthermore the core implements an accurate rate-control that delivers quality practically equivalent to de-facto software encoders. Region of interest coding, progressive streams with multiple quality layers, lossy and lossless compression are JPEG2000 standard benefits also delivered from the JPEG2k-E core.
A single JPEG2k-E core can process mutliple Full HD (1080p@30) channels, as for example it supports an input rate of 190 MSamples/sec when mapped on a 90nm ASIC technology. Users of the core can use parallel instantiations to meet the processing rate requirements even of the most demanding applications.
The JPEG2K-E is a reliable and easy-to-integrate core as it is carefully designed, rigorously verified, and production proven. The architecture can be fine-tuned based on the application specific needs. Ease of integration is served by a complete verification environment, and additional aids for system on chip simulation, such as a software bit-accurate model.
See representative implementation results (each in a new pop-up window):
The JPEG2K-E can be utilized in a variety of digital imaging applications including:
- Digital still cameras and camcorders
- Networked video (Motion JPEG 2000) and image distribution systems
- Wireless video and image distribution systems
- Digital CCTV and surveillance systems
- Image/Video editing systems
- Medical imaging - DICOM
- Military/Aerospace imaging systems
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies. Evaluation boards are available upon request.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- VHDL RTL source code (ASICs) or post-synthesis netlist (FPGAs)
- Sophisticated self-checking Testbench
- Software (C++) Bit accurate model and test vector generator
- Simulation scripts, test vectors, and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
Image Compression Examples
The following samples depict the images and whole-photo file sizes resulting from JPEG 2000 (JP2) and JPEG (JPG) encoding at 20:1 and 75:1 compression levels, and JPEG 2000 Lossless (JP2 LL) encoding.