Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Embedded Processors
BA22 Real-Time Embedded
BA22 Deeply Embedded
BA21 Low Power

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform

 

GPUs & Peripherals
See Graphics &
  Peripherals Cores >

These video and image compression cores and subsystems help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Complement or replace system processors with GPUs and easily integrate memories, peripherals, and hardware networking stacks into SoCs.

NOR Flash Controllers
Serial/SPI NOR Flash
Parallel NOR Flash

Device Controllers
smart card reader

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

AMBA Infrastructure
AMBA Infrastructure Cores
AHB 32-bit DMA


Interconnect Peripherals

See Interconnect Cores >

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

DisplayPort
Transmitter
•  Receiver

Ethernet MAC
•  1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
Hardware RTP Stack for H.264

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

PCI Express
Family Overview
x1/x4
x8
application interface


Data Link Controllers

• SDLC & HDLC

These encryption cores make it easy to build security into a variety of systems.

DES
DES single
DES triple

  • JPEG 2000 compliance
    • Both lossless and lossy compression
    • Error-resilient compression
    • Rate control
    • Headers syntax processing (JPC, JP2, proprietary)
  • Real JPEG2000 Performance
    • No hardware simplification compromises
    • Not based on bypass and parallel mode of entropy coding
    • High-quality, accurate rate-control
    • Region Of Interest
  • Flexible Input Image Format
    • All widely used sub-sampling formats (e.g. 444, 422, etc)
    • Image up to 65,535x65,535
    • Tile size up to 8,192x8,192
    • Up to 4 color components
    • 8 up to 16 bits per sample
  • Programmable JPEG 2000 options
    • 2D-DWT filter type (5/3 or 9/7)
    • Number of 2D-DWT levels
    • Quantization tables
    • Entropy-coding switches (reset, restart, segmark)
    • Input format (pixel depth, image and tile size, number of components, sub-sampling factors)
    • Code-block size (64 or 32 or 16 on each dimension)
    • Up to 30 quality layers
    • Compression ratio per quality layer
  • Tunable architecture during  synthesis
    • Configurable number of entropy coding units
    • Configurable maximum image/tile size
  • Flexible Interfaces
    • 16-bit synchronous SRAM-style host interface
    • Dedicated pixel-in and stream-out interfaces
    • Independent of external memory type (DDR2/3. SDRAM, SRAM, etc.)
    • Glue-less connection to Xilinx, Altera and CAST memory controllers

Contact Sales
Call or click.
+1 201.391.8300

PDF datasheets:

ASIC
Altera, Xilinx

Options:

AHB Compression Core Bus Bridge

Related Products

Compare
Versions

Related information:

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis

 

News Releases

Articles

See the JPEG 2000 entry at Wikipedia.

CAST/Avnet DesignCon paper: A New Reference Design Development Environment for JPEG 2000
(Download Presentation)

News and Info on the JPEG 2000 standard

An Evaluation of Motion JPEG 2000 for Video Archiving (PDF)

Blog Posts

Try it Yourself

cast h.264, ddr2, PCIe IP cores in Virtex-5 demo system

Evaluate this core in hardware with the complete, ready-to-run, JPEG 2000 Application Platform package.

JPEG 2000 IP Core JPEG2K-E JPEG 2000 Compression Encoder Core

The JPEG2K-E core is a complete high performance JPEG2000 - ISO/IEC 15444-1 image compression solution targeted for video and high bandwidth image compression applications.

The JPEG2k-E core delivers real JPEG2000 compression efficiency. Commonly used hardware simplification compromises, such us bypass and parallel mode of the entropy coding process, that damage the JPEG2000 rate-distortion efficiency have not been adopted. Furthermore the core implements an accurate rate-control that delivers quality practically equivalent to de-facto software encoders. Region of interest coding, progressive streams with multiple quality layers, lossy and lossless compression are JPEG2000 standard benefits also delivered from the JPEG2k-E core.

A single JPEG2k-E core can process mutliple Full HD (1080p@30) channels, as for example it supports an input rate of 190 MSamples/sec when mapped on a 90nm ASIC technology. Users of the core can use parallel instantiations to meet the processing rate requirements even of the most demanding applications.

The JPEG2K-E is a reliable and easy-to-integrate core as it is carefully designed, rigorously verified, and production proven. The architecture can be fine-tuned based on the application specific needs.  Ease of integration is served by a complete verification environment, and additional aids for system on chip simulation, such as a software bit-accurate model.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Applications

The JPEG2K-E can be utilized in a variety of digital imaging applications including:

Block Diagram

JPEG2K-E

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.  Evaluation boards are available upon request.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

Image Compression Examples

The following samples depict the images and whole-photo file sizes resulting from JPEG 2000 (JP2) and JPEG (JPG) encoding at 20:1 and 75:1 compression levels, and JPEG 2000 Lossless (JP2 LL) encoding.


2,089 kB

108 kB

28 kB

968 kB
 

108 kB

56 kB