- Highly Efficient Numerically Lossless Compression
- Better compression ratio than most lossless compression algorithms (JPEG2000, PNG, etc.)
- Near-Lossless Compression
- Enables greater compression with visually lossless quality by constraining the maximum difference between reconstructed and original image samples
- Maximum image resolution of 64Kx64K, or higher with via support for oversize image dimension parameters
- Up to 16 bits per color sample; up to four color components
Easy to Use and Integrate
- Run-time programmable input and encoding parameters
- Image resolution, number of color components, color depth
- Maximum reconstruction error, Point-Transform, Local Gradient, Reset Frequency
- Automatic program-once encode-many operation
- AXI4-Stream interfaces for image and compressed data, and 32-bit wide APB for register access
- Dedicated, easy-to-use timestamps interface
Versions and Throughput
Area-optimized JPEG-LS-E-S: one sample per cycle
40,000 eq. gates and up to 500 Msamples/sec on a typical 28nm technology
Throughput optimized JPEG-LS-E-F: synthesis-configurable number of samples per cycle
Source code RTL (Verilog) or Targeted FPGA Netlist
Bit Accurate Model
Sample simulation and synthesis scripts
Call or click.
- HP Labs LOCO-I/JPEG-LS Home Page
- JPEG-LS file viewers: ffplay, IrfanView, XnView
- SDKs supporting JPEG-LS:
– VintaSoft Imaging .NET SDK,
– LEADTOOLS imaging tool kits
- JPEG-LS software implementations:
UBC, ChartLS, Clunie
- Comparison paper (PDF): Lossless Compression of Grayscale Medical Images - Effectiveness of Traditional and State of the Art Approaches
JPEG-LS-E Lossless & Near-Lossless JPEG-LS Encoder
The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard.
Based on LOCO-I (LOw COmplexity LOssless COmpression for Images), the JPEG-LS algorithm leads in numerically lossless compression efficiency, attaining compression ratios similar or superior to those obtained with more advanced algorithms such as JPEG2000. JPEG-LS also enables hardware implementations with a much smaller silicon footprint and lower memory requirements, thanks to its lower computational complexity and line-based processing. Further, the Near-Lossless mode of the JPEG-LS standard makes higher compression ratios and visually lossless compressed images feasible, allowing the user to set the maximum acceptable difference between a reconstructed and an original image sample.
The JPEG-LS-E core delivers the full compression efficiency of the standard in a compact and easy-to-use hardware block. The core interfaces to the system via standardized AMBA® interfaces: it accepts images and outputs compressed data via AXI4-Stream interfaces, and provides access to its control and status registers via a 32-bit APB interface. After its registers are programmed, the core can encode an arbitrary number of images without requiring any further assistance or action from the system. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.
The core is designed with industry best practices, and its reliability has been proven through both rigorous verification and silicon validation. The deliverables include a complete verification environment and a bit-accurate software model.
This core can be mapped to any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
The core is available in two versions: size-optimized JPEG-LS-ES and scalable throughput JPEG-LS-EF. The JPEG-LS-ES version uses just 40K gates, provides a throughput of one sample per cycle, and requires only one image line of buffering. A single JPEG-LS-ES core can compress several hundreds of Msamples per second when mapped on an ASIC technology. The scalable-throughput JPEG-LS-EF version can process multiple samples per cycle by internally aggregating a user-defined number of JPEG-LS-ES cores. It is suitable for compressing images or video with ultra-high resolutions and/or frame rates.
Silicon Resources Utilization
The encoder core can be mapped to any ASIC technology. The JPEG-LS-ES version requires about 40k gates and can run up to 500MHz in a typical 28nm technology. The size of a JPEG-LS-EF version depends on its configuration: please consult with CAST to get accurate characterization data for your target technology and required core configuration.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in source code RTL (Verilog) or as an FPGA netlist, and its deliverables include everything required for successful implementation:
- Sophisticated self-checking Testbench
- Software (C++) Bit-Accurate Model
- Sample simulation and synthesis scripts
- Comprehensive user documentation
The JPEG-LS-E is suitable for systems requiring numerically or visually lossless compression of images or video of potentially high color or greyscale accuracy. Application areas include medical Imaging (DICOM), aerospace imaging or surveillance, and advanced driver assistance systems.
JPEG-LS Compression Efficiency
Despite its lower computational complexity JPEG-LS offers exceptionally high lossless compression efficiency. JPEG-LS is expected to outperform PNG, and to provide similar compression ratios as lossless JPEG 2000 for both color and greyscale images.
The following shows the lossless compression advantage of JPEG-LS over other, more complex algorithms using several indicative example images.
JPEG Cores available from CAST
The JPEG-LS-E is one member of the JPEG family of JPEG encoder and decoder cores that CAST offers. The following table summarizes the family members and highlights their basic features.
|JPEG IP Cores||JPEG-LS IP Cores|
|Compression Standard||JPEG — ISO/IEC 10918-1||JPEG-LS — ISO/IEC 14495-1|
|Supported Standard Modes||Baseline Sequential DCT||Baseline Sequential DCT and Extended Sequential DCT||Lossless& NEAR lossless||Baseline Sequential DCT and Extended Sequential DCT||Lossless & NEAR lossless|
|Motion JPEG Payload|
|Sub-sampling Formats||Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0|
|Max. Image Resolution||64k x 64k||64k x 64k||> 64k x 64k|
|Max. Sample Depth||8||12||12||8||12||12||16|
|Raster Conversion||Included – Optionally Instantiated||Included – Optionally Instantiated||N/A|
|Color Samples/Cycle||1||1||1 to 32||1||1||1 to 32||1 to 32||1 to 32|
|ASIC Area (eq. Gates)||70k||80k||120k1||65k||75k||110k1||40K2||40K2|
|Available in RTL Source Code|
|Available as targeted netlist|
1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample.
2) Silicon Resources for one sample/cycle configuration, and 8 bits per color sample.