JPEG-LS-D Core — ASIC Implementation Results

The JPEG-LS-D can be mapped to any ASIC technology. The size of a core depends on its configuration. The following table provides sample area and performance data for the JPEG-LS-DS core mapped on a typical 16nm technology using SVT cels.

Max. Sample Depth (bits)

Max. NEAR Value

Logic Area

Freq (MHz)

um^2

 Kgates

8
0
6,511
37,681
300
10
0
7,066
40,892
300
16
0
8,581
49,660
300
8
4
7,139
41,315
300
10
4
7,974
46,143
300
16
4
10,023
58,003
300
8
8
7,377
42,689
300
10
8
8,381
48,499
300
16
8
11,036
63,865
280

Note that the list of core configurations is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please consult with CAST to get accurate characterization data for your target technology and required core configuration.

close window