JPEG-LS-D Core — Intel Implementation Results

The JPEG-LS-D can be mapped to any Intel FPGA device, provided enough silicon resources are available. The size of a core depends on its configuration. The following table provides sample area and performance data for the JPEG-LS-D core mapped on an Arria-10 device (speed grade 3) and excludes the image line buffer.

Core Version

Max.  Bits per Sample

Max. NEAR Value

FPGA Resources

MSamples per sec

ALMs

Mem. Bits

JPEG-LS-DS
8
0
5,095
25,046
63
4
5,455
25,046
55
8
5,535
25,046
50
10
0
5,503
30,014
61
4
5,958
30,014
50
8
5,976
30,014
41
16
0
7,767
45,283
77
4
8,479
45,283
37
8
8,492
45,283
31
JPEG-LS-DF with 3 cores
8
0
12,850
75,208
189
10
13,824
90,112
183
16
20,378
135,919
168

Note that the list of core configurations is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please consult with CAST to get accurate characterization data for your target technology and required core configuration.

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