Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

JPEG-LS ISO/IEC 14495-1 Standard Support

  • All JPEG-LS encoding parameters
  • Optional Near Lossless support
  • All interleaved modes
  • All marker segments including APP, COM, DNL and Restart markers
  • Image resolution higher than 64Kx64K (supports oversize image dimension parameters)
  • Up to 16 bits per color sample, and up to four color components

Easy to Use and Integrate

  • Requires no programming or control from host
  • Reports image format
  • Detects and reports marker syntax errors
  • Delivered with bit-accurate software model
  • AXI4-Stream Interfaces for image and compressed data, and 32-bit wide APB for register access
  • Dedicated interface for APP and COM markers to pass metadata to system

Versions and Throughput

  • One sample per cycle, for the area optimized JPEG-LS-DS version
    • From 40,000 eq. gates and up to 350 Msamples/sec on a typical 16nm technology
  • Synthesis-configurable number of samples per cycle, for the throughput optimized JPEG-LS-DF version. Maximum throughput is only possible when images are encoded using restart markers.

Deliverables

  • Source code RTL (Verilog) or targeted FPGA Netlist

  • Bit Accurate Model

  • Sample simulation and synthesis scripts

  • Verification testbenches

  • Comprehensive documentation

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Useful References

Blog Posts

JPEG-LS-D Lossless & Near-Lossless JPEG-LS Decoder

The JPEG-LS-D core implements a highly efficient and low-power, lossless and near-lossless image decompression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard.

The decoder core can decompress any JPEG-LS stream or JPEG-LS payload of image container formats, such as DICOM (Digital Imaging and Communications in Medicine). It accepts compressed streams of images with up to 16-bit per color samples and up to four color components, in all widely used color subsampling formats. Supporting oversize image dimension parameters, the core can decode image with resolutions exceeding 64k x 64k pixels.

The easy-to-use JPEG-LS-D core operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. Application (APP) or comment (COM) marker segments—which are typically used to embed metadata in the compressed stream—are also passed to the system via a dedicated interface.

SoC integration is straightforward thanks to standardized AMBA® interfaces. The core accepts compressed data and outputs pixel data, frame format information, and APP or COM marker segments via AXI4-Stream interfaces, and it provides access to its control and status registers via a 32-bit APB interface. A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core.

 The core is designed with industry best practices, and its reliability has been proven through both rigorous verification and silicon validation. The deliverables include a complete verification environment and a bit-accurate software model.

This core can be mapped to any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Versions

The core is available in two versions, size-optimized and scalable-throughput. The size-optimized version, JPEG-LS-DS, provides a throughput of one sample per cycle and requires only one image line of buffering. A single JPEG-LS-DS core can decompress several hundreds of Msamples per second when mapped on an ASIC technology. The scalable-throughput version, JPEG-LS-DF, can process multiple samples per cycle by internally aggregating a user-defined number of JPEG-LS-DS cores. The JPEG-LS-DF is suitable for compressing images or video with ultra-high resolutions and/or frame rates but assumes the use of restart markers in the encoded stream.

Block Diagram

JPEG-LS-D Lossless & Near-Lossless JPEG-LS Decoder

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in source code RTL (Verilog) or as an FPGA netlist, and its deliverables include everything required for successful implementation:

Applications

The JPEG-LS-D is suitable for applications requiring numerically or visually lossless compression of images or video of potentially high color or greyscale accuracy such as medical Imaging (DICOM), aerospace imaging/surveillance, and advanced driver assistance systems (ADAS).

JPEG-LS Compression Efficiency

Despite its lower computational complexity, JPEG-LS offers exceptionally high lossless compression efficiency. JPEG-LS is expected to outperform PNG, and to provide similar compression ratios as lossless JPEG2000 for both color and greyscale images. Following are some indicative examples: 

JPEG-LS-E Lossless & Near-Lossless JPEG-LS Encoder compression advantage graphic

JPEG Cores available from CAST

The JPEG-LS-D is one member of the JPEG family of JPEG encoder and decoder cores that CAST offers. The following table summarizes the family members and highlights their basic features.

  JPEG IP Cores JPEG-LS IP Cores

JPEG-E-S
Baseline
JPEG Encoder

JPEG-EX-S
Extended
JPEG Encoder

JPEG-EX-F
Ultra Fast Extended
JPEG Encoder

JPEG-D-S
Baseline
JPEG Decoder

JPEG-DX-S
Extended
JPEG Decoder

JPEG-DX-F
Ultra Fast Extended
JPEG Decoder

JPEG-LS-E
JPEG-LS Encoder

JPEG-LS-D
JPEG-LS Decoder

Function Encoder Decoder Encoder Decoder
Compression Type  Lossy Lossless/Lossy
Compression Standard JPEG — ISO/IEC 10918-1 JPEG-LS —  ISO/IEC 14495-1
Supported Standard Modes Baseline Sequential DCT Baseline Sequential DCT and Extended Sequential DCT Lossless& NEAR lossless Baseline Sequential DCT and Extended Sequential DCT Lossless & NEAR lossless
Motion JPEG Payload included included included included included included not supported not supported
Sub-sampling Formats Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0
Max. Image Resolution 64k x 64k 64k x 64k > 64k x 64k
Max. Sample Depth 8 12 12 8 12 12 16
Rate control included included included N/A N/A N/A N/A
Raster Conversion Included – Optionally Instantiated Included – Optionally Instantiated N/A
Color Samples/Cycle 1 1 1 to 32 1 1 1 to 32 1 to 32 1 to 32
ASIC Area  (eq. Gates) 70k 80k 120k1 65k 75k 110k1 40K2 40K2
Available in RTL Source Code not supported included included not supported included included included included
Available as targeted netlist included included included included included included included included

Notes:

1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample.

2) Silicon Resources for one sample/cycle configuration, and 8 bits per color sample.

 

 

 

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