JPEG-EX-S Core — Lattice Implementation Results

The JPEG-EX-S core can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core. Note that the implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology.

Family /

Device
Logic Block RAMs

DSP

Comp.

Fmax

(MHz)
ECP5U / LAE5U-12F

8.380 Slices

12,945 LUT4s
11
8
95

close window