- ISO/IEC 10918-1 Standard Baseline and Extended Encoder (Sequential DCT modes)
- Single-frame JPEG images and Motion JPEG payloads
- 8-bit and 12-bit per color samples
- Up to four color components; any image size up to 64k x 64k
- All scan configurations and all JPEG formats
- APP, COM, and restart markers
- Programmable Huffman Tables and Quantization tables
Rate Control Options
- Image: Limits the size of each individual frame
- Video: Regulates bit rate over a number of input frames
- AXI Streaming I/O data interfaces
- APB Control/Status interface
Performance and Size
- One encoded sample per clock cycle
- Small silicon footprint (about 80k ASIC gates)
Ease of Integration
- Automatic program-once/encode-many operation
- Simple, dedicated timestamps interface
- Included bit-accurate software model generates test vectors, expected results, and core programming values
- Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer
Call or click.
JPEG Lossy Encoders
JPEG Lossy Decoders
- JPEG-LS-E Lossless & Near-Lossless JPEG-LS Encoder
See the JPEG entry at Wikipedia.
See the Motion JPEG entry at Wikipedia.
JPEG-EX-S Baseline and Extended JPEG Encoder
This JPEG compression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, ASIC or FPGA hardware JPEG encoder with very low processing latency.
The JPEG-EX-S Encoder produces compressed JPEG images and the video payload for Motion JPEG container formats. It accepts images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.
The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it requires just 80,000 equivalent gates when mapped on an ASIC technology.
Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.
Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.
The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
The JPEG-EX-S core’s low processing latency and ability to regulate compressed image size or video bit rate make it ideal for video streaming systems even in the presence of strict bandwidth and latency limitations. Suitable applications include:
Consumer electronics or professional imaging products such as digital cameras, camcorders, and office automation equipment (printers, scanners, etc.).
Residential, corporate, airborne, and other security or surveillance systems.
Machine vision and video links for industrial, defense, or other systems.
Medical imaging systems, and advanced driver assistance systems.
Silicon Resources Utilization
The JPEG-EX-S Encoder core synthesizes to approximately 80K gates and requires 16k to 30k-bits of memory, depend-ing on tis configuration.
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- Verilog RTL source code
- Sophisticated self-checking Testbench
- Software (C++) Bit-Accurate Model
- Sample simulation and synthesis scripts
- Comprehensive user documentation
JPEG Cores available from CAST
The JPEG-EX-S is one member of the JPEG family of JPEG encoder and decoder cores that CAST offers. The following table summarizes the family members and highlights their basic features.
|JPEG IP Cores||JPEG-LS IP Cores|
|Compression Standard||JPEG — ISO/IEC 10918-1||JPEG-LS —
|Supported Standard Modes||Baseline Sequential DCT||Baseline Sequential DCT and Extended Sequential DCT||Lossless& NEAR lossless||Baseline Sequential DCT and Extended Sequential DCT||Lossless & NEAR lossless|
|Motion JPEG Payload|
|Sub-sampling Formats||Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0|
|Max. Image Resolution||64k x 64k||64k x 64k||> 64k x 64k|
|Max. Sample Depth||8||12||12||8||12||12||16|
|Raster Conversion||Included – Optionally Instantiated||Included – Optionally Instantiated||N/A|
|Color Samples/Cycle||1||1||1 to 32||1||1||1 to 32||1|
|ASIC Area (eq. Gates)||70k||80k||120k1||65k||75k||110k1||From 40K2|
|Available in RTL Source Code|
|Available as targeted netlist|
1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample.
2) Silicon Resources for one sample/cycle configuration, and 8 bits per color sample.