JPEG-EX-F Ultra-Fast, 4K/8K, Baseline and Extended JPEG Encoder

This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less power than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG2000. 

The JPEG-EX-F Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats.

Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame video.

Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.

Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):

Applications

The JPEG-EX-F core is suitable for systems supporting ultra-high frame resolutions and/or frame rates, such as:

• Corporate, airborne, and other security or surveillance systems.

• Machine vision and video link decoders or terminals for industrial, or defense systems.

• Medical imaging systems.

Block Diagram

Silicon Resources Utilization

The silicon resources requirements for the JPEG-EX-F encoder core depend on its configuration. The default two samples per cycle configuration synthesizes to approximately 120K gates and requires 50k bits of memory.

Verification

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• Verilog RTL source code
• Sophisticated self-checking Testbench
• Software (C++) Bit-Accurate Model
• Sample simulation and synthesis scripts
• Comprehensive user documentation

Comparing Still Image Compression Cores

	JPEG IP Cores						JPEG-LS IP Cores
	JPEG-E-S Baseline JPEG Encoder	JPEG-EX-S Extended JPEG Encoder	JPEG-EX-F Ultra Fast Extended JPEG Encoder	JPEG-D-S Baseline JPEG Decoder	JPEG-DX-S Extended JPEG Decoder	JPEG-DX-F Ultra Fast Extended JPEG Decoder	JPEG-LS-E JPEG-LS Encoder	JPEG-LS-D JPEG-LS Decoder
Function	Encoder			Decoder			Encoder	Decoder
Compression Type	Lossy						Lossless/Lossy
Compression Standard	JPEG — ISO/IEC 10918-1						JPEG-LS —  ISO/IEC 14495-1
Supported Standard Modes	Baseline Sequential DCT	Baseline Sequential DCT and Extended Sequential DCT		Lossless& NEAR lossless	Baseline Sequential DCT and Extended Sequential DCT		Lossless & NEAR lossless
Motion JPEG Payload
Sub-sampling Formats	Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0
Max. Image Resolution	64k x 64k			64k x 64k			> 64k x 64k
Max. Sample Depth	8	12	12	8	12	12	16
Rate control				N/A	N/A	N/A	N/A
Raster Conversion	Included – Optionally Instantiated			Included – Optionally Instantiated			N/A
Color Samples/Cycle	1	1	1 to 32	1	1	1 to 32	1 to 32	1 to 32
ASIC Area  (eq. Gates)	70k	80k	120k1	65k	75k	110k1	40K2	40K2
Available in RTL Source Code
Available as targeted netlist
Notes: 1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample. 2) Silicon Resources for one sample/cycle configuration, and 8 bits per color sample.