Pre-layout results reported from synthesis tool and silicon vendor design kit under typical conditions with all core I/Os assumed to be routed on-chip. Implementation numbers are for the core optimized for speed.
| ASIC Technology |
Logic Eq. Gates |
Fmax |
Memory |
| UMC 0.18µ process |
54,500 |
300 MHz |
16,448 bits |
| TSMC 0.18µ process |
61,000 |
300 MHz |
16,448 bits |
| TSMC 90nm process |
49,000 |
500 MHz |
16,448 bits |
| TSMC 65nm process |
58,200 |
750 MHz |
16,448 bits |