JPEG IP Core JPEG-E Baseline Compression JPEG Encoder Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables | Related Cores

The JPEG-E core is a standalone and high-performance JPEG encoder for still image and video compression applications.

One of the fastest available JPEG cores, the JPEG-E can encode multiple Full HD channels even in low-cost FPGA devices.  Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes the JPEG-E core ideal for interoperable systems and devices.In addition to generating standalone Baseline JPEG streams, the core is also capable of producing the (de facto) standard video payload of many motion JPEG container formats. The JPEG-E can also be enhanced with an optional add-on bit-rate control block, which may benefit applications that have tight bandwidth constraints.

Evaluation designs show that the core has a small footprint, requiring, for example, approximately 50,000 equivalent gates and 16kbits of internal memory for a 90nmn implementation. Furthermore it easily fits most of the low-cost FPGA devices. Its heavily optimized architecture enables a very high performance, reaching processing rates of up to 750 MSamples/sec in a 65nm technology.

The core is designed with easy to use, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and production-proven, the JPEG-E is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.

See representative implementation results (each in a new pop-up window):

Features

Baseline ISO/IEC 10918-1 JPEG Compliance

• Programmable Huffman Tables (two DC, two AC)
• Programmable quantization tables (up to four)
• Up to four color components
• Supports all possible scan configurations and all JPEG formats for input and output data
• Supports any image size up to 64k x 64k
• Supports DNL and restart markers
• Standalone, Baseline JPEG stream output

Additional Image Processing Capabilities

• Motion JPEG payload encoding
• Rate-Control (optional)

Designed for Easy Integration

• Simple and zero latency streaming interfaces
• Single clock per input sample for encoding
• Fully programmable through standard JPEG stream marker segments
• Automatic JPEG markers headers generation on the output
• Automatic program-once encode-many operation

Designed for High Quality

• Robust verification environment includes bit-accurate software model
• ASIC and FPGA proven in multiple designs

Applications

The high-performance JPEG-E core is suitable for implementing a variety of digital imaging applications, including:

• Digital cameras and camcorders
• Office automation equipment (multifunction printers, etc)
• Medical imaging systems
• Video conference systems
• Surveillance systems

Block Diagram

Functional Description

The JPEG-E is configured by feeding it with JPEG headers, which contain table specification data, image format definitions, and encoding options. The core’s configuration can be optionally modified after the encoding of one or more frames. The image samples in any color space are input to the JPEG-E in a MCU block scan order.

Consuming a single clock cycle per input image sample, the JPEG-E can address the most demanding frame-based video compression applications. The JPEG-E outputs a complete JPEG-compliant data stream, including JPEG headers, the size of which can be dynamically controlled if the optional rate-control block is utilized.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive synthesis, place and route, and simulation rubs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies. The core has been verified through extensive synthesis, place and route, and simulation rubs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis netlist (FPGAs)
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
• Software (C++) Bit-Accurate Model and test vector gene-rator
• Simulation script, test vectors, and expected results
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

Related Cores

• JPEG-E-X Baseline/Extended Sequential JPEG Encoder – adds support for 12 bits per sample
• SVE-JPEG-E SpeedView Enabled JPEG Encoder that produces SpeedView enabled JPEG data streams.
• CMMI-JPEG Multimedia Interface – adds an AHB interface to the JPEG-E core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables | Related Cores

Download PDF datasheets for more info: ASIC | Actel | Altera | Lattice | Xilinx