Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

BA22 32-bit Processors
Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Embedded Processors
BA22 Real-Time Embedded
BA22 Deeply Embedded
BA21 Low Power

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform
AMBA Infrastructure Cores
AHB 32-bit DMA

Other Peripherals
See Interconnects &
Peripherals Cores >

These video and image compression cores help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Block/Raster Converters
block-to-raster
raster-to-block
raster-block bidirect

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Functions & Converters
Color Space Converter

Video Deinterlacers
Basic

Quickly complete the standrd parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores. Choose high-speed DisplayPort or PCI Express, Ethernet MACs, the CAN bus for automotive systems, and more.

High-Speed Serial
PCI Express
Family Overview
x1/x4
x8
application interface

Parallel
ECP slave
ATA/IDE interface

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

TCP/IP Stacks
UDP/IP stack

Ethernet MAC
Device Controllers

10/100
10/100 lite
Gigabit
Gigabit lite
Gigabit PCS

MAC Platforms
MAC/PCI

Customers find these cores to be an excellent solution for preserving existing product board designs when critical chips are no longer available for purchase.

 
80186XL
80186EC
80188EC
80251
387L math

DSPs
32025 16-bit
32025TX 16-bit

 

 

Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Cores for integrating security, controlling devices and displays, and other SoC functions.

Device Controllers
smart card reader

IR Remote Controls
RC5
NEC

Audio Interfaces
I2S-SC
I2S-MC
SPDIF

Baseline ISO/IEC 10918-1 JPEG Compliance

  • Programmable Huffman Tables (two DC, two AC)
  • Programmable quantization tables (up to four)
  • Up to four color components
  • Supports all possible scan configurations and all JPEG formats for input and output data
  • Supports any image size up to 64k x 64k
  • Supports DNL and restart markers
  • Standalone, Baseline JPEG stream output

Additional Image Processing Capabilities

  • Programmable Quantization Quality (1 to 100)
  • Motion JPEG payload encoding
  • One-pass compression ratio regulation (optional)
    • Motion JPEG video oriented rate control option with programmable nominal output frame size and transmission buffer size in bytes
    • Block-based, rate control option with independent Luminance and Chrominance thresholds

Designed for Easy Integration

  • Simple, microcontroller like, programming interface
  • Avalon-ST I/O data interfaces
  • Optional AHB or AXI bus interfaces
  • Single clock per input sample for encoding
  • Fully programmable through standard JPEG stream marker segments
  • Automatic JPEG markers headers generation on the output
  • Automatic program-once encode-many operation

Designed for High Quality

  • Robust verification environment includes bit-accurate software model
  • ASIC and FPGA proven in multiple designs

Contact Sales
Call or click.
+1 800.391.8300

PDF Datasheets

ASIC
Actel, Altera, Lattice, Xilinx

Options

AHB Compression Core Bus Bridge

Related Products

Compare
Versions

  • JPEG-C Baseline JPEG Compression Codec
  • JPEG-D Baseline JPEG Compression Decoder
  • JPEG-E-X Baseline/Extended Sequential 12-bit DICOM JPEG Encoder
  • SVE-JPEG-E Scalado SpeedView JPEG Encoder
  • CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the JPEG-E core

Customer Comments

Fastec's TS3 high-speed camera uses CAST JPEG IP core"The quality of the core plus CAST's determination to see us succeed were both instrumental in bringing our groundbreaking handheld high-speed camera, the TS3, to market on time and on spec.
    The JPEG encoder's features and excellent performance were as specified, and the system integration was so easy I didn't need CAST's technical support services.
   The sales team also went above and beyond, first in making sure we got the Fastec Imaging uses CAST IP Coresright IP product, then with flexible terms that worked with our project requirements."
— Bob Sefton, Principal FPGA Design Engineer, Fastec Imaging Corp.

See sample slow-motion videos from the TS3 on Fastec's YouTube channel, including this one.

 

Related Information

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis

 

News Releases

Technology Info

See the JPEG entry at Wikipedia.

JPEG IP Core JPEG-E Baseline Compression JPEG Encoder Core

The JPEG-E core is a standalone and high-performance JPEG encoder for still image and video compression applications.

One of the fastest available JPEG cores, the JPEG-E can encode multiple Full HD channels even in low-cost FPGA devices.  Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes the JPEG-E core ideal for interoperable systems and devices.In addition to generating standalone Baseline JPEG streams, the core is also capable of producing the (de facto) standard video payload of many motion JPEG container formats. The JPEG-E can also be enhanced with an optional add-on bit-rate control block, which may benefit applications that have tight bandwidth constraints.

Evaluation designs show that the core has a small footprint, requiring, for example, approximately 50,000 equivalent gates and 16kbits of internal memory for a 90nmn implementation. Furthermore it easily fits most of the low-cost FPGA devices. Its heavily optimized architecture enables a very high performance, reaching processing rates of up to 750 MSamples/sec in a 65nm technology.

The core is designed with easy to use, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and production-proven, the JPEG-E is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.

See representative implementation results (each in a new pop-up window):

ASIC numbersActel numbers Altera numbersLattice numbersXilinx numbers

Applications

The high-performance JPEG-E core is suitable for implementing a variety of digital imaging applications, including:

Block Diagram

JPEG-E Baseline JPEG Encoder Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive synthesis, place and route, and simulation rubs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies. The core has been verified through extensive synthesis, place and route, and simulation rubs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

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