Baseline/Extended Sequential ISO/IEC 10918-1 JPEG Compliance
- Programmable Huffman Tables (two DC, two AC) and
- Programmable quantization tables (four)
- Up to four color components
- All possible scan configurations and all JPEG formats for input/output data
- Image sizes up to 64k x 64k
- DNL and restart markers
Additional Image Processing Capabilities
- Programmable Quantization Quality (1 to 100)
- Motion JPEG payload encoding
- Digital Imaging Communication in Medicine (DICOM) standard conformance
- One-pass compression ratio regulation (optional)
- Motion JPEG video oriented rate control option with programmable nominal output frame size and transmission buffer size in bytes
- Block-based, rate control option with independent Luminance and Chrominance thresholds
Designed for Easy Integration
- Simple, microcontroller like, programming interface
- Avalon-ST I/O data interfaces
- Optional AHB or AXI bus interfaces
- Single clock per input sample for encoding
- Fully programmable through standard JPEG stream marker segments
- Automatic JPEG markers headers generation on the output
- Automatic program-once encode-many operation
Designed for High Quality
- Robust verification environment includes bit-accurate software model
- Scan-ready design architecture
- ASIC and FPGA proven in multiple designs
Call or click.
- JPEG-C Baseline JPEG Compression Codec
- JPEG-D Baseline JPEG Compression Decoder
- JPEG-E Baseline Compression JPEG Encoder
- SVE-JPEG-E Scalado SpeedView JPEG Encoder
- CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the JPEG-E-X core
See the JPEG entry at Wikipedia.
JPEG IP Core JPEG-E-X Baseline & Extended JPEG Encoder Core
The JPEG-E-X core implements a high-performance image encoder that complies with both the Baseline (8-bit) and Extended Sequential (12-bit) DCT modes of the ISO/IEC 10918-1 JPEG standard.
One of the fastest available Extended JPEG encoders, the JPEG-E-X can encode at Full HD (1080p30) or higher rates, even in FPGA devices. Full compliance with the Baseline and the Extended Sequential DCT modes of the ISO/IEC 10918-1 JPEG standard makes the JPEG-E-X core ideal for interoperable systems and devices such as consumer digital cameras, camcorders, office automation equipment, medical imaging systems, video conference systems and remote surveillance systems.
The produced JPEG streams conform also to the Digital Imaging and Communications in Medicine (DICOM) requirements. In addition to generating standalone Baseline or Extended JPEG streams, the core is also capable of producing the (de facto) standard video payload of many motion JPEG container formats. Furthermore, bandwidth-constraint applications may benefit from the included programmable bit-rate control block.
The core includes FIFO-like pixel and stream input/output interfaces. Other standard interfaces (e.g. AMBA) are available. The core is designed for reliability and ease of integration, and has been proven in a number of ASIC and FPGA designs. The deliverables include a software bit-accurate model that facilitates system on chip verification.
The core includes FIFO-like pixel and stream input/output interfaces. Other standard interfaces (e.g. AMBA) are available. The core is designed for reliability and ease of integration, and has been proven in a number of ASIC and FPGA designs. The deliverables include a complete verification environment and software bit-accurate model.
See representative implementation results (each in a new pop-up window):
The high-performance, compact JPEG-E-X core is suitable for applications needing lossy compression but requiring exceptional image detail, including:
- Digital cameras and camcorders
- Office automation equipment (multifunction printers, digital copiers etc)
- Medical imaging systems
- Video production suites
- Video conference and display projection systems
- Surveillance systems
- Portable multimedia devices (smart-phones, tablets, PDAs etc)
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive simulation and rigorous code coverage measurements. It has also been proven in FPGA technologies.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- Simulation script, vectors, expected results, and comparison utility
- Software (C++) Bit-Accurate Model
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications
and a system integration guide