JPEG IP Core JPEG-E-X Baseline & Extended JPEG Encoder Core

The JPEG-E-X core implements a high-performance image encoder that complies with both the Baseline (8-bit) and Extended Sequential (12-bit) DCT modes of the ISO/IEC 10918-1 JPEG standard.

One of the fastest available Extended JPEG encoders, the JPEG-E-X can encode at Full HD (1080p30) or higher rates, even in FPGA devices. Full compliance with the Baseline and the Extended Sequential DCT modes of the ISO/IEC 10918-1 JPEG standard makes the JPEG-E-X core ideal for interoperable systems and devices such as consumer digital cameras, camcorders, office automation equipment, medical imaging systems, video conference systems and remote surveillance systems.

The produced JPEG streams conform also to the Digital Imaging and Communications in Medicine (DICOM) requirements. In addition to generating standalone Baseline or Extended JPEG streams, the core is also capable of producing the (de facto) standard video payload of many motion JPEG container formats. Furthermore, bandwidth-constraint applications may benefit from the included programmable bit-rate control block.

The core includes FIFO-like pixel and stream input/output interfaces. Other standard interfaces (e.g. AMBA) are available. The core is designed for reliability and ease of integration, and has been proven in a number of ASIC and FPGA designs. The deliverables include a software bit-accurate model that facilitates system on chip verification.

The core includes FIFO-like pixel and stream input/output interfaces. Other standard interfaces (e.g. AMBA) are available. The core is designed for reliability and ease of integration, and has been proven in a number of ASIC and FPGA designs. The deliverables include a complete verification environment and software bit-accurate model.

See representative implementation results (each in a new pop-up window):

Applications

The high-performance, compact JPEG-E-X core is suitable for applications needing lossy compression but requiring exceptional image detail, including:

• Digital cameras and camcorders
• Office automation equipment (multifunction printers, digital copiers etc)
• Medical imaging systems
• Video production suites
• Video conference and display projection systems
• Surveillance systems
• Portable multimedia devices (smart-phones, tablets, PDAs etc)

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. It has also been proven in FPGA technologies.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
• Simulation script, vectors, expected results, and comparison utility
• Software (C++) Bit-Accurate Model
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide