Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Performs Baseline Sequential DCT JPEG encoding of images or video for ASICs or FPGAs, with small silicon area, high performance, and low latency.

Standards Support

  • ISO/IEC 10918-1 Standard Baseline Encoder  (Sequential DCT modes)
  • Encodes single-frame JPEG images and Motion JPEG payloads
  • 8-bit per color samples
  • Up to four color components; any image size up to 64k x 64k
  • Handles all scan configurations and all JPEG formats
  • APP, COM, and restart markers
  • Programmable Huffman Tables and Quantization tables

Rate Control Options

  • Image: Limits the size of each individual frame
  • Video: Regulates bit rate over a number of input frames

Interfaces

  • AXI Streaming I/O data interfaces
  • APB Control/Status interface
  • Optional AHB wrapper with DMA capabilities

Performance and Size

  • One encoded sample per clock cycle
  • Small silicon footprint (about 70k ASIC gates)

Ease of Integration

  • Automatic program-once/encode-many operation
  • Simple, dedicated timestamps interface
  • Included bit-accurate software model generates test vectors, expected results, and core programming values
  • Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer

Format

  • Available as a netlist for ASICs or FPGAs

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Compare
Versions

  • JPEG-EX-S Baseline and Extended JPEG Encoder Core
  • JPEG-EX-F Ultra-Fast Baseline and Extended JPEG Encoder Core
  • JPEG-D-S Baseline JPEG Decoder Core
  • JPEG-DX-S Baseline and Extended JPEG Decoder
  • JPEG-DX-F Ultra-Fast Baseline and Extended JPEG Decoder Core
  • UDPIP-1G/10G UDP/IP Hardware Protocol Stack
  • JPEG2RTP Hardware RTP Stack for JPEG

News Releases

Articles

See the JPEG entry at Wikipedia.

See the  Motion JPEG entry  at Wikipedia.

Blog Posts

JPEG-E-S Baseline JPEG Encoder

This JPEG compression IP core supports the Baseline Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, ASIC or FPGA, hardware JPEG encoder with remarkably low processing latency.

The JPEG-E-S Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats.

The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it requires about 70,000 equivalent gates when mapped on an ASIC technology.

Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.

Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Applications

The JPEG-E-S core’s low processing latency and ability to regulate compressed image size or video bit rate make it ideal for video streaming systems even in the presence of strict bandwidth and latency limitations. Suitable applications include:

Block Diagram

JPEG-E-S Baseline JPEG Encoder Core  Block Diagram

Silicon Resources Utilization

The JPEG-E-S Encoder core synthesizes to approximately 70K gates and requires 16k to 30k bits of memory, depending on its configuration.

Verification

The core has been verified through extensive synthesis, place and route, and simulation runs. It has been embedded in several shipping customer products, and is proven in both ASIC and FPGA technologies.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available as a targeted netlist for ASICs and FPGAs, and includes everything required for successful implementation. The deliverable package includes:

JPEG Cores available from CAST

The JPEG-E-S is one member of the JPEG family of JPEG encoder and decoder cores that CAST offers. The following table sum-marizes the family members and highlights their basic features.

 

JPEG-E-S
Baseline JPEG Encoder

JPEG-EX-S
Extended JPEG Encoder

JPEG-EX-F
Ultra Fast Ext. JPEG Encoder

JPEG-D-S
Baseline JPEG Decoder

JPEG-DX-S
Extended JPEG Decoder

JPEG-DX-F
Ultra Fast Ext. JPEG Decoder

Functionality Encoder Decoder
Baseline JPEG included included included included included included
Extended Sequential JPEG not supported included included not supported included included
Motion JPEG Payload included included included included included included
Sub-sampling Formats Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0
Image Resolution 16x16 to 64k x 64k
Max. Sample Depth 8 12 12 8 12 12
Rate control included included included N/A N/A N/A
Raster Conversion Included – Optionally Instantiated
Color Samples/Cycle 1 1 1 to 32 1 1 1 to 32
ASIC Area  (eq. Gates) 70k 80k 120k1 65k 75k 110k1
Available in RTL Source Code not supported included included not supported included included
Available as targeted netlist included included included included included included
1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample

 

 

 

 

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