Area-efficient, high-performance 8/12-bit JPEG decoder for ASICs and FPGAs
- ISO/IEC 10918-1 Standard Baseline and Extended Decoder (Sequential DCT modes)
- Single-frame JPEG images and Motion JPEG payloads
- Up to four color components
- 8- and 12-bit color samples
- All widely used color-sub-sampling formats, and any image size up to 64k x 64k
- All scan configurations and all JPEG formats
- All marker segments expect DNL
- Up to four Huffman Tables
- Up to four b-nit or 18-bit Quantization tables
- AXI Streaming I/O data interfaces
- APB Control/Status interface
- Optional AHB wrapper with DMA capabilities
Performance and Size
- One decoded sample per clock cycle
- Small silicon footprint (~75k Gates)
Ease of Integration
- Requires no programming or control from host
- Reports image format
- Detects and reports marker syntax errors
- Delivered with bit-accurate software model
- Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer
Call or click.
- JPEG-E-S Baseline JPEG Encoder Core
- JPEG-EX-S Baseline and Extended JPEG Encoder Core
- JPEG-EX-F Ultra-Fast Baseline and Extended JPEG Encoder Core
- JPEG-D-S Baseline JPEG Decoder Core
- JPEG-DX-F Ultra-Fast Baseline and Extended JPEG Decoder Core
- UDPIP-1G/10G UDP/IP Hardware Protocol Stack
- JPEG2RTP Hardware RTP Stack for JPEG
See the JPEG entry at Wikipedia.
See the Motion JPEG entry at Wikipedia.
JPEG-DX-S Baseline and Extended JPEG Decoder
The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard.
It decompresses JPEG images, and also video payload for Motion-JPEG container formats. It supports 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. The decoder processes one color sample per clock cycle, enabling it to process multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG decoders available, it requires just 75,000 equivalent gates when mapped on an ASIC technology.
Once programmed, the easy-to-use encoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.
SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.
Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.
The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.
See representative implementation results (each in a new pop-up window):
The JPEG-DX-S core’s excellent performance and low silicon resource usage make it suitable for implementing a variety of digital imaging applications, including:
Residential, corporate, airborne, and other security or surveillance systems.
Machine vision and video link decoders/terminals for industrial, defense, or other systems.
Medical imaging system, and advanced driver assistance systems.
Silicon Resources Utilization
The JPEG-DX-S core synthesizes to approximately 75K gates and requires 25k bits of memory.
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- Verilog RTL source code
- Sophisticated self-checking Testbench
- Software (C++) Bit-Accurate Model
- Sample simulation and synthesis scripts
- Comprehensive user documentation
JPEG Cores available from CAST
The JPEG-DX-S is a member of the JPEG family of cores that CAST offers. The following table summarizes the family members and highlights their basic features.
|Extended Sequential JPEG|
|Motion JPEG Payload|
|Sub-sampling Formats||Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0|
|Image Resolution||16x16 to 64k x 64k|
|Max. Sample Depth||8||12||12||8||12||12|
|Raster Conversion||Included – Optionally Instantiated|
|Color Samples/Cycle||1||1||1 to 32||1||1||1 to 32|
|ASIC Area (eq. Gates)||70k||80k||120k1||65k||75k||110k1|
|Available in RTL Source Code|
|Available as targeted netlist|
|1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample|