JPEG-DX-F Core — Lattice Implementation Results

The JPEG-DX-F can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data the core configured to process 2 pixels per cycle (JPEG-DX-F/2) and under its default configuration. Note that the implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology.

Family / Device Logic

Block

RAMs

DSP

Comp.

Fmax

(MHz)
ECP5U / LAE5U-12F

18.250 LUT4s

12,904 Slices
18 16 70

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