Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

8/12-bit JPEG decoder for ASIC and FPGA with scalable, ultra-high performance

Standards Support

  • ISO/IEC 10918-1 Standard Baseline and Extended Decoder  (Sequential DCT modes)
  • Single-frame JPEG images and Motion JPEG payloads
  • Up to four color components
  • 8- and 12-bit color samples
  • All widely used color-sub-sampling formats, and any image size up to 64k x 64k
  • All scan configurations and all JPEG formats
  • All marker segments expect DNL
  • Up to four Huffman Tables
  • Up to four b-nit or 18-bit Quantization tables

Interfaces

  • AXI Streaming I/O data interfaces
  • APB Control/Status interface
  • Optional AHB wrapper with DMA capabilities

Performance

  • Synthesis-time configurable scalable architecture
  • Very high throughput: up to 32 samples per clock cycle
  • Achieves maximum throughput when decoding streams produced by JPEG-EX-F

Ease of Integration

  • Requires no programming or control from host
  • Reports image format
  • Detects and reports marker syntax errors
  • Delivered with bit-accurate software model
  • Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer

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Articles

See the JPEG entry at Wikipedia.

See the  Motion JPEG entry  at Wikipedia.

Blog Posts

JPEG-DX-F Ultra-Fast Baseline and Extended JPEG Decoder

This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates.

The JPEG-DX-F Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.

Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-EX-F Encoder Core. This Encoder-Decoder pair provide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.

Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.

Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

See representative implementation results (each in a new pop-up window):

Altera numbers Xilinx numbers

Applications

The JPEG-DX-F core’s great throughput makes it suitable for systems supporting ultra-high frame resolutions and/or frame rates, such as:

Block Diagram

JPEG-DX-F Ultra-Fast Baseline and Extended JPEG Decoder  Blcok Diagram

Silicon Resources Utilization

The silicon resources requirements for the JPEG-DX-F en-coder core depend on its configuration. A two samples per cycle configuration synthesizes to approximately 110K gates and requires 50k-bits of memory.

Verification

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

JPEG Cores available from CAST

The JPEG-DX-F is a member of the JPEG family of cores that CAST offers. The following table summarizes the family members and highlights their basic features.

 

JPEG-E-S
Baseline JPEG Encoder

JPEG-EX-S
Extended JPEG Encoder

JPEG-EX-F
Ultra Fast Ext. JPEG Encoder

JPEG-D-S
Baseline JPEG Decoder

JPEG-DX-S
Extended JPEG Decoder

JPEG-DX-F
Ultra Fast Ext. JPEG Decoder

Functionality Encoder Decoder
Baseline JPEG included included included included included included
Extended Sequential JPEG not supported included included not supported included included
Motion JPEG Payload included included included included included included
Sub-sampling Formats Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0
Image Resolution 16x16 to 64k x 64k
Max. Sample Depth 8 12 12 8 12 12
Rate control included included included N/A N/A N/A
Raster Conversion Included – Optionally Instantiated
Color Samples/Cycle 1 1 1 to 32 1 1 1 to 32
ASIC Area  (eq. Gates) 70k 80k 120k1 65k 75k 110k1
Available in RTL Source Code not supported included included not supported included included
Available as targeted netlist included included included included included included
1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample

 

 

 

 

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