Pre-layout results reported from synthesis tool and silicon vendor design kit under typical conditions. Implementation numbers are for the core optimized for speed.
| ASIC Technology |
Logic Eq. Gates |
Fmax |
Memory |
| UMC 0.18µ process |
68,459 |
300 MHz |
14,400 bits |
| TSMC 0.09µ process |
61,061 |
450 MHz |
14,400 bits |