Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform


GPUs & Peripherals
See Graphics &
  Peripherals Cores >

These video and image compression cores and subsystems help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
J2K Platform

Lossless Image Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Lossless Data Compression
ZipAccel Compression
ZipAccel Decompression

Complement or replace system processors with GPUs and easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Graphics Processors
Nema Embedded GPU
ThinkVG vector GPU
2D/2.5D Graphic Accelerator

Display Controllers
Multilayer LCD Display Processor

Device Controllers
smart card reader

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

AMBA Infrastructure
AMBA Infrastructure Cores
AHB 32-bit DMA

Interconnect Peripherals

See Interconnect Cores >

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

• Receiver

Ethernet MAC
• 1G eMAC Controller

Data Link Controllers

PCI — Target
32-bit multi
PCI — Master
32-bit multi
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

DES single
DES triple

Baseline ISO/IEC 10918-1 JPEG Compliance

  • Up to four Huffman Tables
  • Up to four quantization tables
  • Up to four color components
  • Supports all possible scan configurations and all JPEG formats for input and output data
  • Supports any image size up to 64k x 64k
  • Supports DNL and restart markers

Additional Image Processing Capabilities

  • Motion JPEG payload decoding

Designed for Easy Integration

  • Stand alone operation
  • Automatic self-programming by JPEG stream markers parsing
  • Marker errors catching
  • Broadcasting of decoded image parameters for controlling peripherals such as a block-to-raster scan converter
  • Optional block-to-raster conversion

Designed for High Quality

  • Robust verification environment includes bit-accurate software model
  • ASIC and FPGA proven in multiple designs

Contact Sales
Call or click.
+1 201.391.8300

PDF Datasheets

Microsemi, Altera, Lattice, Xilinx


AHB Compression Core Bus Bridge

Related Products


  • JPEG-C Baseline JPEG Compression Codec
  • JPEG-E Baseline Compression JPEG Encoder
  • JPEG-D-X Baseline & Extended JPEG Decoder Core
  • JPEG-E-X Baseline/Extended Sequential 12-bit DICOM JPEG Encoder
  • SVE-JPEG-E Scalado SpeedView JPEG Encoder
  • CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the JPEG-D core.

Related Information

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis


News Releases


See the JPEG entry at Wikipedia.

Blog Posts

JPEG-D Baseline JPEG Compression Decoder Core

The JPEG-D core is a standalone and high-performance JPEG decoder for still image and video decompression applications.

One of the fastest available JPEG decoders, the JPEG-D can decode at Full HD (1080p@30) or higher rates, even in low-cost FPGA devices. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes the JPEG-D core ideal for interoperable systems and devices. In addition to decoding standard Baseline JPEG streams, the core is also capable of decompressing the video payload of many (de facto) standard motion JPEG container formats.

Evaluation designs show that the core has a small footprint, requiring, for example, approximately 61,000 equivalent gates and 14kbits of internal memory for a 90nmn implementation. Its heavily optimized architecture enables a very high performance, reaching processing rates of up to 450 MSamples/sec in a 90nm technology.

The core is designed with easy to use, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and production-proven, the JPEG-D is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.

See representative implementation results (each in a new pop-up window):

ASIC numbers Microsemi numbers Altera numbersLattice numbers Xilinx numbers


The high-performance JPEG-D core is suitable for implementing a variety of digital imaging applications, including:

Block Diagram

JPEG-D Baseline JPEG Decoder Blcok Diagram


The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


The core has been verified through extensive synthesis, place and route, and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.


The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation: