Baseline ISO/IEC 10918-1 JPEG Compliance
- Up to four Huffman Tables
- Up to four quantization tables
- Up to four color components
- Supports all possible scan configurations and all JPEG formats for input and output data
- Supports any image size up to 64k x 64k
- Supports DNL and restart markers
Additional Image Processing Capabilities
- Motion JPEG payload decoding
Designed for Easy Integration
- Stand alone operation
- Automatic self-programming by JPEG stream markers parsing
- Marker errors catching
- Broadcasting of decoded image parameters for controlling peripherals such as a block-to-raster scan converter
Designed for High Quality
- Robust verification environment includes bit-accurate software model
- ASIC and FPGA proven in multiple designs
Call or click.
- JPEG-C Baseline JPEG Compression Codec
- JPEG-E Baseline Compression JPEG Encoder
- JPEG-E-X Baseline/Extended Sequential 12-bit DICOM JPEG Encoder
- SVE-JPEG-E Scalado SpeedView JPEG Encoder
- CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the JPEG-D core.
- 09/09/05, CAST Joins LSI Logic RapidChip® Platform ASIC IP Partner Program
- 02/02/04, CAST Introduces Flexible Family of JPEG IP Cores
- 05/29/02, CAST Releases JPEG Cores
See the JPEG entry at Wikipedia.
JPEG IP Core JPEG-D Baseline JPEG Compression Decoder Core
The JPEG-D core is a standalone and high-performance JPEG decoder for still image and video decompression applications.
One of the fastest available JPEG decoders, the JPEG-D can decode at Full HD (1080p@30) or higher rates, even in low-cost FPGA devices. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes the JPEG-D core ideal for interoperable systems and devices. In addition to decoding standard Baseline JPEG streams, the core is also capable of decompressing the video payload of many (de facto) standard motion JPEG container formats.
Evaluation designs show that the core has a small footprint, requiring, for example, approximately 61,000 equivalent gates and 14kbits of internal memory for a 90nmn implementation. Its heavily optimized architecture enables a very high performance, reaching processing rates of up to 450 MSamples/sec in a 90nm technology.
The core is designed with easy to use, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and production-proven, the JPEG-D is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.
See representative implementation results (each in a new pop-up window):
The high-performance JPEG-D core is suitable for implementing a variety of digital imaging applications, including:
- Home entertainment devices (set-top boxes, network media players etc)
- Portable multimedia devices (media players, mobile phones etc)
- Digital printing devices
- Medical imaging systems
- Video conference systems
- Surveillance systems
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive synthesis, place and route, and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis netlist (FPGAs)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- Software (C++) Bit-Accurate Model and test vector generator
- Simulation scripts, test vectors and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide