JPEG IP Core JPEG-D Baseline JPEG Compression Decoder Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

Implements a high-performance image or video decoder that complies with the baseline ISO/IEC 10918-1 JPEG standard.

One of the fastest available JPEG cores, the JPEG-D provides a high-performance solution for a variety of image and video decompression applications. It can, for example, decode 16:9 HDTV, 1920x1152, 4:2:0, even in FPGA devices. In a typical 0.09µ process ASIC, the core requires just 61,000 gates and operates at 450 MHz.

In addition to processing baseline JPEG streams, the core can decompress non-standard motion JPEG streams. It can also be enhanced with an optional IDCT block that enables down-scaling in the frequency domain, a feature that allows decompression at various resolutions from the same compressed stream.

The core includes FIFO-like pixel and stream input/output interfaces, and other standard interfaces (e.g. AMBA) are also available. The core is designed for reliability and ease of integration, and has been proven in a number of ASIC and FPGA designs. The deliverables include a software bit-accurate model that facilitates system on chip verification.

See representative implementation results (each in a new pop-up window):

Features

Baseline ISO/IEC 10918-1 JPEG Compliance

• Programmable Huffman Tables (two DC, two AC) and
• Programmable quantization tables (four)
• Up to four color components (optionally extendable to 255 components)
• Supports all possible scan configurations and all JPEG formats for input/output data
• Supports any image size up to 64k x 64k
• Supports DNL and restart markers

Additional Image Processing Capabilities

• Motion JPEG decoding
• Decompressing at various resolutions via downscaling in the frequency domain (optional)

Designed for Easy Integration

• Stand alone operation
• Automatic self-programming by JPEG stream headers parsing
• Header errors catching
• Broadcasting of decoded image parameters for controlling peripherals such as a raster to block converter

Designed for High Quality

• Robust verification environment includes bit-accurate software model
• ASIC and FPGA proven in multiple designs
• Scan-ready design architecture

Applications

The high-performance JPEG-D core is suitable for implementing a variety of multimedia applications, including:

• Digital cameras and camcorders
• Office automation equipment (multifunction printers, scanners, digital copiers etc)
• Medical imaging systems
• Video production suites
• Video conference and display-projection systems
• Surveillance systems

Block Diagram

Functional Description

The decoding path is highly autonomous, since the JPEG-D is self-configured (with table, image format and encoding options) by parsing the incoming JPEG stream’s headers. The core parses and checks all JPEG marker segments and signals in case it detects an error. Decoded image parameters are made available for controlling peripherals such as a block-to-raster converter.

Designed for continuous data flow, the JPEG-D can address the most demanding frame-based video decompression applications. Optional decoding at various resolutions from the same JPEG data-stream without the need for any extra buffering is enabled when the IDCT block is configured during synthesis to support downscaling in the frequency domain.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Software (C++) Bit-Accurate Model
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

 

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Actel | Altera | Lattice | Xilinx

 

  This core developed by the multimedia experts at Alma Technologies S.A.