JPEG-D-S Core — XILINX FPGA Results

The JPEG-D-S can be mapped to any Xilinx Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core. Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology.

 

1080p30

4:4:4

1080p60

4:2:0

1080p60

4:2:2
LUTs DSPs BRAMs

Artix-7 (-2)

included included not supported 6,800 5 2 RAMB16

Kintex7 (-2)

included included included 6,100 5 2 RAMB16

Kintex7-US (-1)

included included included 5,900 5 2 RAMB16

 

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