Area-efficient, high-performance Baseline JPEG decoder for ASIC and FPGA
- ISO/IEC 10918-1 Standard Baseline Decoder
- Single-frame JPEG images and Motion JPEG payloads
- Up to four color components
- 8-bit color samples
- All widely used color-sub-sampling formats, and any image size up to 64k x 64k
- All scan configurations and all JPEG formats
- All marker segments expect DNL
- Up to four Huffman Tables
- Up to four b-nit or 18-bit Quantization tables
- AXI Streaming I/O data interfaces
- APB Control/Status interface
- Optional AHB wrapper with DMA capabilities
Performance and Size
- One decoded sample per clock cycle
- Small silicon footprint (~65k Gates)
Ease of Integration
- Requires no programming or control from host
- Reports image format
- Detects and reports marker syntax errors
- Delivered with bit-accurate software model
- Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer
- Available as a netlist for ASICs or FPGAs
Call or click.
JPEG Lossy Encoders
- JPEG-E-S Baseline JPEG Encoder Core
- JPEG-EX-S Baseline and Extended
- JPEG-EX-F Ultra-Fast Baseline and Extended
JPEG Lossy Decoders
- JPEG-LS-E Lossless & Near-Lossless JPEG-LS Encoder
See the JPEG entry at Wikipedia.
See the Motion JPEG entry at Wikipedia.
JPEG-D-S Baseline JPEG Decoder
This JPEG decompression IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It implements a high-performance, ASIC or FPGA, hardware JPEG encoder that is very small in silicon area.
The JPEG-D-S Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats.
The decoder processes one color sample per clock cycle, enabling it to process multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG decoders available, it requires just 65,000 equivalent gates when mapped on an ASIC technology.
Once programmed, the easy-to-use encoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.
SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.
Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.
The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
The JPEG-D-S core’s excellent performance and low silicon resource usage make it suitable for implementing a variety of digital imaging applications, including:
- Residential, corporate, airborne, and other security or surveillance systems.
- Machine vision and video link decoders/terminals for industrial, defense, or other systems.
- Medical imaging system, and advanced driver assistance systems.
Silicon Resources Utilization
The JPEG-D-S Encoder core synthesizes to approximately 65K gates and requires 20k bits of memory.
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in ASIC and FPGA forms, and includes everything required for successful implementation. The ASIC version includes:
- Sophisticated self-checking Testbench
- Software (C++) Bit-Accurate Model
- Sample simulation and synthesis scripts
- Comprehensive user documentation
JPEG Cores available from CAST
The JPEG-D-S is a member of the JPEG family of cores that CAST offers. The following table summarizes the family members and highlights their basic features.
|JPEG IP Cores||JPEG-LS IP Cores|
|Compression Standard||JPEG — ISO/IEC 10918-1||JPEG-LS —
|Supported Standard Modes||Baseline Sequential DCT||Baseline Sequential DCT and Extended Sequential DCT||Lossless& NEAR lossless||Baseline Sequential DCT and Extended Sequential DCT||Lossless & NEAR lossless|
|Motion JPEG Payload|
|Sub-sampling Formats||Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0|
|Max. Image Resolution||64k x 64k||64k x 64k||> 64k x 64k|
|Max. Sample Depth||8||12||12||8||12||12||16|
|Raster Conversion||Included – Optionally Instantiated||Included – Optionally Instantiated||N/A|
|Color Samples/Cycle||1||1||1 to 32||1||1||1 to 32||1|
|ASIC Area (eq. Gates)||70k||80k||120k1||65k||75k||110k1||From 40K2|
|Available in RTL Source Code|
|Available as targeted netlist|
1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample.
2) Silicon Resources for one sample/cycle configuration, and 8 bits per color sample.