Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

MIPI
SPMI Master/Slave

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Area-efficient, high-performance Baseline JPEG decoder for ASIC and FPGA

Standards Support

  • ISO/IEC 10918-1 Standard Baseline Decoder
  • Single-frame JPEG images and Motion JPEG payloads
  • Up to four color components
  • 8-bit color samples
  • All widely used color-sub-sampling formats, and any image size up to 64k x 64k
  • All scan configurations and all JPEG formats
  • All marker segments expect DNL
  • Up to four Huffman Tables
  • Up to four b-nit or 18-bit Quantization tables

Interfaces

  • AXI Streaming I/O data interfaces
  • APB Control/Status interface
  • Optional AHB wrapper with DMA capabilities

Performance and Size

  • One decoded sample per clock cycle
  • Small silicon footprint (~65k Gates)

Ease of Integration

  • Requires no programming or control from host
  • Reports image format
  • Detects and reports marker syntax errors
  • Delivered with bit-accurate software model
  • Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer

Format

  • Available as a netlist for ASICs or FPGAs

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

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Versions

JPEG Lossy Encoders

JPEG Lossy Decoders

JPEG-LS Lossless/Lossy

  • JPEG-LS-E Lossless & Near-Lossless JPEG-LS Encoder

Network Stacks

News Releases

Articles

See the JPEG entry at Wikipedia.

See the  Motion JPEG entry  at Wikipedia.

Blog Posts

JPEG-D-S Baseline JPEG Decoder

This JPEG decompression IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It implements a high-performance, ASIC or FPGA, hardware JPEG encoder that is very small in silicon area.

The JPEG-D-S Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats.

The decoder processes one color sample per clock cycle, enabling it to process multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG decoders available, it requires just 65,000 equivalent gates when mapped on an ASIC technology.

Once programmed, the easy-to-use encoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.

Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):

Altera numbers Xilinx numbers

Applications

The JPEG-D-S core’s excellent performance and low silicon resource usage make it suitable for implementing a variety of digital imaging applications, including:

Block Diagram

JPEG-D-S Baseline and Extended JPEG Decoder Block Diagram

Silicon Resources Utilization

The JPEG-D-S Encoder core synthesizes to approximately 65K gates and requires 20k bits of memory.

Verification

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in ASIC and FPGA forms, and includes everything required for successful implementation. The ASIC version includes:

JPEG Cores available from CAST

The JPEG-D-S is a member of the JPEG family of cores that CAST offers. The following table summarizes the family members and highlights their basic features.

  JPEG IP Cores JPEG-LS IP Cores

JPEG-E-S
Baseline
JPEG Encoder

JPEG-EX-S
Extended
JPEG Encoder

JPEG-EX-F
Ultra Fast Extended
JPEG Encoder

JPEG-D-S
Baseline
JPEG Decoder

JPEG-DX-S
Extended
JPEG Decoder

JPEG-DX-F
Ultra Fast Extended
JPEG Decoder

JPEG-LS-E
JPEG-LS Encoder

JPEG-LS-D
JPEG-LS Decoder

Function Encoder Decoder Encoder Decoder
Compression Type  Lossy Lossless/Lossy
Compression Standard JPEG — ISO/IEC 10918-1 JPEG-LS —  ISO/IEC 14495-1
Supported Standard Modes Baseline Sequential DCT Baseline Sequential DCT and Extended Sequential DCT Lossless& NEAR lossless Baseline Sequential DCT and Extended Sequential DCT Lossless & NEAR lossless
Motion JPEG Payload included included included included included included not supported not supported
Sub-sampling Formats Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0
Max. Image Resolution 64k x 64k 64k x 64k > 64k x 64k
Max. Sample Depth 8 12 12 8 12 12 16
Rate control included included included N/A N/A N/A N/A
Raster Conversion Included – Optionally Instantiated Included – Optionally Instantiated N/A
Color Samples/Cycle 1 1 1 to 32 1 1 1 to 32 1 to 32 1 to 32
ASIC Area  (eq. Gates) 70k 80k 120k1 65k 75k 110k1 40K2 40K2
Available in RTL Source Code not supported included included not supported included included included included
Available as targeted netlist included included included included included included included included

Notes:

1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample.

2) Silicon Resources for one sample/cycle configuration, and 8 bits per color sample.

 

 

 

 

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