Baseline ISO/IEC 10918-1 JPEG Compliance
- Programmable Huffman Tables (two DC, two AC)
- Programmable quantization tables (up to four)
- Up to four color components
- Supports all possible scan configurations and all JPEG formats for input and output data
- Any image size up to 64k x 64k
- Supports DNL and restart markers
Additional Image Processing Capabilities
- Motion JPEG payload encoding and decoding
- Rate-Control (optional)
Designed for Easy Integration
- Standalone operation
- Simple and zero latency streaming interfaces
- Encoding Mode
- Single clock per input sample
- Fully programmable through standard JPEG stream marker segments
- Automatic headers generation
- Automatic program-once encode-many operation
- Decoding Mode
- Automatic self-programming by JPEG markers parsing
- Marker errors catching
- Broadcasting of decoded image parameters for controlling peripherals such as raster to block converter
Designed for High Quality
- Robust verification environment includes bit-accurate software model
- ASIC and FPGA proven in multiple designs
Call or click.
- JPEG-D Baseline JPEG Compression Decoder
- JPEG-E Baseline Compression JPEG Encoder
- JPEG-E-X Baseline/Extended Sequential 12-bit DICOM JPEG Encoder
- SVE-JPEG-E Scalado SpeedView JPEG Encoder
- CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the JPEG-C core
- 09/09/05, CAST Joins LSI Logic RapidChip® Platform ASIC IP Partner Program
- 02/02/04, CAST Introduces Flexible Family of JPEG IP Cores
See the JPEG entry at Wikipedia.
JPEG IP Core JPEG-C Baseline JPEG Compression Codec Core
The JPEG-C core is a standalone and high-performance, half-duplex, JPEG codec for still image and video compression applications.
One of the fastest available JPEG codecs, the JPEG-C can process multiple Full HD channels, even in FPGA devices. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes the JPEG-C core ideal for interoperable systems and devices. In addition to the standard Baseline JPEG streams, the core is also capable of supporting the video payload of many (de facto) standard motion JPEG container formats. The JPEG-C can also be enhanced with an optional add-on bit-rate control block, which will benefit the bandwidth constraint applications.
Evaluation designs show that the core fits in a variety of silicon technologies, requiring, for example, approximately 95,000 gates on a 90nm process. Its heavily optimized architecture enables a very high performance, reaching processing rates beyond 300 MSamples/sec.
The core is designed with easy to use, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and production-proven, the JPEG-C is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.
See representative implementation results (each in a new pop-up window):
The JPEG-C can be utilized for a variety of digital imaging applications including:
- Office automation equipment (Multi-function printers, scanners, etc)
- Digital cameras & camcorders
- Medical imaging systems
- Video conference systems
- Surveillance systems
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- Software (C++) Bit-Accurate Model and test vector generator
- Simulation scripts, test vectors and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide