SHA-3 Core — XILINX FPGA Results

Sample implementation results for the minimum throughput configuration of the core implemented on a Kintex UltraScale+ (speed grade -1) device are provided in the following table. Note that the figures on this table do not represent the highest clock frequency or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology.

Hash Function

LUTs

BRAMs

Freq. (MHz)

Gbps

SHA3-224

6,123

0

400

19.20

SHA3-256

6,008

0

400

18.13

SHA3-384

5,495

0

400

13.87

SHA3-512

4,926

0

400

9.60

SHAKE-128

6,523

0

400

22.40

SHAKE-256

6,044

0

400

18.13

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