SHA-3 ASIC Implementation Results

Sample implementation results for the minimum throughput configuration of the core implemented on a 28nm technology (TSMC hpm-sc9-svt-c31) are provided in the following table. Please contact CAST to get characterization data for your target configuration and technology.

Area (Gates)

Freq.
(MHz)

Number of In. Buffers

SHA3-224

SHA-256

SHA3-384

SHA3-512

SHAKE-128

SHAKE-256

33.3k

30.0k

29.1k

27.8k

32.5k

30.4k

700

0

48.3k

46.8k

42.8k

38.8k

52.6k

47.6k

700

2

Note that these sample implementation figures do not represent the highest speed or smallest area possible for the core.

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