SHA-3 Core — Intel Implementation Results

Sample implementation results for the minimum throughput configuration of the core implemented on an Arria10 (speed grade -2) device are provided in the following table. Please contact CAST to get characterization data for your target configuration and technology.

Area (ALMs)

Freq.
(MHz)

Number of
In. Buffers

SHA3-224

SHA-256

SHA3-384

SHA3-512

SHAKE- 128

SHAKE- 256

3,350

3,256

2,907

2,698

3,605

3,311

250

0

3,869

3,748

3,328

3,135

4,315

3,819

275

2

Note that these sample implementation figures do not represent the highest speed or smallest area possible for the core.

 

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