SHA-256 Core Xilinx Implementation Results

The SHA-256 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family

LUTs

BRAMs

Freq.
(MHz)

Throughput (Gbps)

Virtex-7 (-3)
1,183
0
350
 2.757
Virtex UltraScale (-3)
1,224
0
400
 3.151
Kintex UltraScale (-1)
1,265
0
350
2,757
Kintex UltraScale+ (-1)
1,268
0
400
3,151

 

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