SHA-256 ASIC Implementation Results

The SHA-256 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughput (Gbps)

TSMC 40nm
 29,985
 800
 6.302
TSMC 28nm HPM
14,674
1,000
3.938
TSMC 16nm
 17,963
1,400
11.028

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