CAST SHA256 Core ASIC Implementation Results

Results with all I/Os assumed to be routed off-chip using I/O registers. Results are optimized for speed with equivalent gates count using the smallest NAND2 gate available in the technology.

Technology

Fmax
(MHz)
Logic Area
(um2)

Number of
eq. gates

UMC 0.18 µm

280 250,040


20.5 K

TSMC 0.09 µm

500 50,800

18.0 K

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