SHA-256 Core Intel Implementation Results

The SHA-256 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Intel results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family

ALMs

RAM bits

Freq.
(MHz)

Throughput (Mbps)

MAX 10 (-7)
2,068
0
125
895
Arria 10 GX (-1)
893
0
125
895
Stratix V (-3)
901
0
200
1,575
Stratix V (-1)
900
0
225
1,772

 

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