- Designed according to the FIPS 180-2 Standard
- Maximum message length up to (264 – 1) bits
- Suitable for data authentication application
- Simple, fully synchronous, reusable design
- Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
- Complete deliverables include test benches, C model and test vector generator
SHA-256 256-bit SHA Cryptoprocessor Core
The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits.
Developed for easy reuse in ASIC and FPGA applications, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for the AMBA bus interface is available as an option.
SHA-256 reference designs have been evaluated in a variety of technologies. See representative implementation results (in a new pop-up window):
The SHA-256 can be utilized for a variety of encryption applications including:
Electronic Funds Transfer
Authenticated Electronic data transfer
Encrypted data storage
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in FPGA technologies.
This core implements encryption functions and as such it is subject to export control regulations. Export to your country may or may not require a special export license. Please contact CAST to determine what applies in your specific case.
The core is available in ASIC (RTL) or FPGA (netlist) forms, and includes everything required for successful implementation.
- HDLRTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Sophisticated HDL Testbench (self checking)
C Model & test vector generator
Simulation script, vectors & expected results