The SHA-1 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

SHA-1 Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq.
(MHz)

Throughout (Mbps)

Virtex-7 (-3)
1,044
0
300
1,896
Kintex-7 (-2)
868
0
150
948
Kintex UltraScale (-2)
1,043
0
250
1,580
Kintex UltraScale (-1)
843
0
200
1,264
Kintex UltraScale+ (-1)
838
0
350
2,212

 

close window