SHA-1 ASIC Implementation Results

The SHA-1 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

ASIC Technology

Number of
eq. gates

Fmax
(MHz)

Throughout (Gbps)

TSMC 16nm
10,642
500
3.160
TSMC 28nm HPM
10,286
500
3.160

TSMC 40nm G

12,838
500
3.160

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