The SHA-1 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Intel results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

SHA-1 Core Intel Implementation Results

Family

ALMs

RAM bits

Freq.
(MHz)

Throughout (Mbps)

Arria 10 GX (-2)
632
224
150
948
Stratix V (-1)
678
0
325
2,054
MAX 10 (-7)
1,018
160
100
632

 

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