Security IP Core SHA1 Secure Hash Algorithm Core

The SHA1 core is a high-performance implementation of the SHA-1 Secure Hash message digest Algorithm. This one-way hash function conforms to the 1995 US Federal Information Processing Standard (FIPS) 180-1. It accepts a large, variable-length message and produces a fixed-length message authorization code.

The core is composed of two main modules, the SHA1 Engine Module and the Input Interface Module as shown in the block diagram. The SHA1 Engine Module applies the SHA1 loops on a single 512-bit message block, while the Input Interface Module performs the message padding. The processing of one 512-bit block is performed in 82 clock cycles, and the bit-rate achieved is 6.24Mbps/MHz on the input of the SHA1core.

The SHA1 core is equipped with fully-stallable input and output interfaces. These enable the user’s application to stop the input stream according to a data arrival rate, or to stop the output stream when the core is not able to receive data.

The core has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs. Representative results show it to produce a competitive implementation, running at 350 MHz and requiring just 14,500 gates in a .18 µm ASIC process. The complete deliverables feature comprehensive documentation, and a bit-accurate software model (BAM).

See representative implementation results (each in a new pop-up window):

Applications

The core is suitable for a variety of applications requiring digital signatures or other  message origin authentication or tamper protection, including:

• E-commerce
• Data integrity
• Bulk Encryption
• High-speed networking equipment
• Secure wireless applications

Block Diagram

Support

The SHA1 core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The SHA1 core has been verified through extensive simulation and rigorous code coverage measurements. It has also been verified in a prototyping FPGA board platform.

Export Permits

This encryption technology is governed internationally by export regulations. Immediate export of the core is permitted to the following countries for uses not related to weapons of mass destruction:

Argentina	Russia
Australia	South Korea
Canada	Switzerland
European Union Member States	Turkey
Japan	Ukraine
New Zealand	United States
Norway

Please contact CAST to discuss delivery to other destinations; approval is subject to the applicable export licenses being granted. The license can be generated from either the EU or the USA. Please note that licensees are responsible for complying with the applicable requirements for re-export of electronics containing strong encryption technology.

Deliverables

The SHA1 is available as a soft core (synthesizable HDL) for ASIC technologies and as a firm core (netlist) for FPGA technologies, and includes everything required for successful implementation. The Asic version includes:

• HDL (VHDL or Verilog) RTL source code.
• Synthesis scripts.
• Simulation script, vectors and expected results.
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001).
• Software (C++) Bit-Accurate Model.
• Comprehensive user documentation, including detailed specifications and a system integration guide.