Security IP Core MD5 Message Digest Processor Core

The MD5 core is a high performance implementation of the MD5 Message Digest algorithm, a one-way hash function, compliant with RFC1321.  The core is composed of two main modules, the MD5 Engine Module and the Input Interface Module as shown in the block diagram.  The MD5 Engine Module applies the MD5 loops on a single 512-bit message block, while the Input Interface Module performs the message padding.

The processing of one 512-bit block is performed in 66 clock cycles and the bit-rate achieved is 7.75Mbps / MHz on the input of the MD5 engine.

The MD5 core is equipped with easy to use fully stallable interfaces both for input and output. These are designed to permit the user’s application to stop the data stream from the core when it is not able to receive data or to stop the input stream towards the core according to data arrival rate.

See representative implementation results (each in a new pop-up window):

Applications

The high-performance MD5 core is suitable for a variety of applications, including:

• E-commerce
• Data integrity
• Bulk Encryption
• High speed networking equipment
• Secure wireless applications

Block Diagram

Support

The MD5 core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The MD5 core has been verified through extensive simulation and rigorous code coverage measurements. It has also been verified in a prototyping FPGA board platform.

Export Permits

This encryption technology is governed internationally by export regulations. Immediate export of the core is permitted to the following countries for uses not related to weapons of mass destruction:

Argentina	Russia
Australia	South Korea
Canada	Switzerland
European Union Member States	Turkey
Japan	Ukraine
New Zealand	United States
Norway

Please contact CAST to discuss delivery to other destinations; approval is subject to the applicable export licenses being granted. The license can be generated from either the EU or the USA. Please note that licensees are responsible for complying with the applicable requirements for re-export of electronics containing strong encryption technology.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL (VHDL or Verilog) RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Synthesis script (ASICs) or place and route script (FPGAs)
• Simulation script, vectors and expected results
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
• Software (C++) Bit-Accurate Model
• Comprehensive user documentation, including detailed specifications and a system integration guide