- Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
- Employs user-programmable key size of 128, 192 or 256 bits
- Two architectural versions:
- Standard is more compact: 32-bit data path size
- Fast yields higher transmission rates: 128-bit data path
- Suitable for use with AES cores
- Simple, fully synchronous, reusable design
- Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
- Complete deliverables include test benches, C model and test vector generator
Call or click.
- AES Advanced Encryption Standard Core
- AES-P Programmable Advanced Encryption Standard Core
- AES-CCM AES CCM Advanced Encryption Standard Core
- AES-GCM AES GCM Authenticated Encrypt/Decrypt Core
AES Core Links
FIPS 197, Advanced Encryption Standard (AES): download PDF
AES test suite: The Advanced Encryption Standard Algorithm Validation Suite (AESAVS): download PDF
KEXPKey Expander Core
The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P and AES-GCM cores. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.
Two architectural versions are available to suit system requirements. The Standard version is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block.
The KEXP core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
IEXP reference designs have been evaluated in a variety of technologies. See representative implementation results (in a new pop-up window):
The KEXP can be utilized for a variety of encryption applications including:
- Protected network routers
- Electronic financial transactions
- Secure wireless communications
- Secure video surveillance systems
- Encrypted data storage
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been em-bedded in several products, and is proven in FPGA technologies.
This core implements encryption functions and as such it is subject to export control regulations. Export to your country may or may not require a special export license. Please contact CAST to determine what applies in your specific case.
The core is available in ASIC (RTL) or FPGA (netlist) forms, and includes everything required for successful implementation.
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Sophisticated HDL Testbench (self checking)
C Model & test vector generator
Simulation script, vectors & expected results
Comparing AES Encryption/Decryption Cores
|Run time Programmable Encryption or Decryption operation||yes||yes||yes||yes|
|Run-time Programmagle Cipher-Key length||yes||yes||yes||yes|
|Run-time Programmable Block Cipher mode||no||yes||no||no|
|Number of cycles per data block 128/192/256 key||44/52/60 or 11/13/15||44/52/60 or 11/13/15||44/52/60 or 11/13/15||44/52/60 or 11/13/15|
* only one encryption/deceryption mode supported by each release of the core