Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform

 

GPUs & Peripherals
See Graphics &
  Peripherals Cores >

These video and image compression cores and subsystems help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Complement or replace system processors with GPUs and easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Graphics Processors
Nema Embedded GPU
ThinkVG vector GPU
2D/2.5D Graphic Accelerator

Display Controllers
Multilayer LCD Display Processor

Device Controllers
smart card reader

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

AMBA Infrastructure
AMBA Infrastructure Cores
AHB 32-bit DMA


Interconnect Peripherals

See Interconnect Cores >

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

DisplayPort
Transmitter
• Receiver

Ethernet MAC
• 1G eMAC Controller

Data Link Controllers
• SDLC & HDLC

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

DES
DES single
DES triple

  • FIPS 46-3 Standard Compliant
  • Encryption/Decryption performed in 48 cycles(ECB mode)
  • Up to 168 bits of security
  • For use in FPGA or ASIC designs
  • Verilog IP Core

Non Pipelined version

  • Small gate count shared DES

Pipelined version

  • Pipelined for maximum performance
  • Encryption/Decryption performed in 1 cycle (ECB mode) after an initial latency of 48 cycles

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PDF Datasheets

ASIC
Altera, Xilinx

Related Products

Related Information

White Paper
AES Encryption and CAST’s AES IP Cores (PDF)

Security Core DES3 Triple Data Encryption Standard Core

The DES3 core implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.

The DES3 core is a block cipher, working on 64 bits of data at a time. It is built upon the Data Encryption Standard (DES) core. Key length is 64 bits of which only 56 bits are used. The DES3 core uses three independent keys. Encoding and decoding operations are performed in 48 clocks per block, in Electronic Codebook (ECB) mode.

The DES3 core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs.  The DES3 IP Core is delivered as Verilog RTL Source code.

The DES3 Low Gate version is implemented to minimize gate count or FPGA resources.  The design does not use any memories such as SRAM. 

The DES3 Pipelined version is implemented to maximize performance by pipelining the DES algorithm through three DES-PL instantiations.  After an initial latency of 48 cycles, it can output encryption/decryption at every cycle. The design does not use any memories such as SRAM. 

See representative implementation results (each in a new pop-up window):

ASIC numbersAltera numbersXilinx numbers

Applications

The DES3 core can be utilized for a variety of encryption applications including::

Block Diagrams

DES3 Non-Pipelined Block DES3 Pipelined Block

Example of DES3 Encryption AND Decryption Operations

The following is an example that may be used when testing the DES3 encryption and decryption operations. In this example, all keys, plaintext and ciphertext are expressed in hexadecimal. The example uses three independent keys, which are:

Key1 = 0123456789ABCDEF
Key2 = 23456789ABCDEF01
Key3 = 456789ABCDEF0123

The plaintext for the example is selected from the ASCII encoding of the phrase “The quick brown fox jumped over the lazy dog’s back”. The example employs the first 24 characters of the phrase (i.e., The quick brown fox jump).

The ASCII encoding of the above phrase is segmented as follows:

“The quic”
5468652071756663
“k brown ”
6B2062726F776E20
“fox jump”
666F78206A756D70
DES3 Block Cipher Encryption Operation - ECB Mode

In the example below, the input and output of the DES engine are given sequentially. 

Note that DES1, DES2 and DES3 represent the three passes through the DES engine.

The input to DES1 is PlainText P1, and the output of DES1 is “A28E91724C4BBA31”. The input to DES2 is the output of DES1, and the output of DES2 is “5A2EA7F983A2F53F”. The input to DES3 is the output of DES2, and the output of DES3 is “A826FD8CE53B855F”. The output of DES3 is the ciphertext C1.

P1 = “The quic” = 5468652071756663

Input
Output
DES1 – Encrypt – Key1 
5468652071756663
A28E91724C4BBA31
DES2 – Decrypt – Key2
A28E91724C4BBA31
5A2EA7F983A2F53F
DES3 – Encrypt – Key3
5A2EA7F983A2F53F
A826FD8CE53B855F

C1 = A826FD8CE53B855F

During the second DES3 operation, the input is P2, and the output after the three passes is ciphertext C2.

P2 = “k brown ” = 6B2062726F776E20

Input
Output
DES1 – Encrypt – Key1
6B2062726F776E20
167E47EC24F71D63
DES2 – Decrypt – Key2
167E47EC24F71D63
EA141A7DD69701F0
DES3 – Encrypt – Key3
EA141A7DD69701F0
CCE21C8112256FE6

C2 = CCE21C8112256FE6

During the third DES3 operation, the input is P3, and the output after the three passes is ciphertext C3.

P3 = “ fox jump” = 666F78206A756D70

Input
Output
DES1 – Encrypt – Key1
666F78206A756D70
2C1A917234425365
DES2 – Decrypt – Key2
2C1A917234425365
8059EE8212E22A79
DES3 – Encrypt – Key3
8059EE8212E22A79
68D5C05DD9B6B900

C3 = 68D5C05DD9B6B900

The resulting ciphertext is the concatenation of C1, C2 and C3 (i.e., A826FD8CE53B855F CCE21C8112256FE6 68D5C05DD9B6B900).

DES3 Block Cipher Decryption Operation - ECB Mode

During decryption operations in ECB mode, the ciphertext C1, C2 and C3 (section from 3.1) are fed into the DES3 to produce the plaintext P1, P2 and P3. The output of DES1 becomes the input to DES2, and the output of DES2 becomes the input to DES3.

C1 = A826FD8CE53B855F

Input
Output
DES1 – decrypt - Key3
A826FD8CE53B855F
5A2EA7F983A2F53F
DES2 – encrypt - Key2
5A2EA7F983A2F53F
A28E91724C4BBA31
DES3 – decrypt - Key1
A28E91724C4BBA31
5468652071756663

P1 = 5468652071756663 = “The quic”.

C2 = CCE21C8112256FE6

Input
Output
DES1 – decrypt – Key3
CCE21C8112256FE6
EA141A7DD69701F0
DES2 – encrypt – Key2
EA141A7DD69701F0
167E47EC24F71D63
DES3 – decrypt – Key1
167E47EC24F71D63
6B2062726F776E20

P2 = 6B2062726F776E20 = “k brown ”

C3 = 68D5C05DD9B6B900

Input
Output
DES1 – decrypt – Key3
68D5C05DD9B6B900
8059EE8212E22A79
DES2 – encrypt – Key2
8059EE8212E22A79
2C1A917234425365
DES3 – decrypt – Key1
2C1A917234425365
666F78206A756D70

P3 = 666F78206A756D70= “fox jump”.

The plaintext is the ASCII encoding of “The quick brown fox jump”.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation: