DES3 Core — XILINX FPGA Results

The DES3 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following tables provide sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Non Pipelined Optimized for Speed

Xilinx Device

Slices

BRAM
I/Os

Fmax
(MHz)

Throughput
(Mbps)

ISE
Spartan-3E
3S1200E-5
742 - 302 101 134 12.2i
Spartan-6
6SLX25-3
339 - 302 143 190 12.2i
Virtex-4
4VLX15-12
1072 - 302 175 233 9.2.04i
Virtex-5
5VLX30-3
257 - 302 221 294 12.2i
Virtex-6
6VLX130T-3
256 - 302 290 386 12.2i

Pipelined Optimized for Speed

Xilinx Device

Slices

BRAM
I/Os

Fmax
(MHz)

Throughput
(Gbps)

ISE
Spartan-3E
3S1200E-5
7111 - 302 143 9.15 12.2i
Spartan-6
6SLX25-3
2148 - 302 179 11.45 12.2i
Virtex-4
4VLX15-12
5691 - 302 194 12.41 9.2.04i
Virtex-5
5VLX85-2
2405 - 302 320 20.48 12.2i
Virtex-6
6VLX130T-3
2034 - 302 329 21.05 12.2i

 

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