DES3 ASIC Implementation Results

The DES3 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following tables provide sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Non Piplined Optimized for Area

ASIC Technology

Cell
Area

NAND2 Area Used

Approx. Area
(gate equiv.)
Frequency
(MHz)

Throughput (Mbps)

TSMC .09 µm 10,746 2.82 3,810 450 1800
TSMC .13 µm 21,801 5.0922 4,281 262 1048
TSMC .18 µm 44,550 9.9792 4,472 155 620

Non Pipelined Optimized for Speed

ASIC Technology

Cell
Area

NAND2 Area Used

Approx. Area
(gate equiv.)
Frequency
(MHz)

Throughput (Gbps)

TSMC .09 µm 15,383 2.82 5,455 909 3.63
TSMC .13 µm 36,215 5.0922 7,112 581 2.32
TSMC .18 µm 71,101 9.9792 7,124 469 1.87

Pipelined Optimized for Speed

ASIC Technology

Cell
Area

NAND2 Area Used

Approx. Area
(gate equiv.)
Frequency
(MHz)

Throughput (Gbps)

TSMC .09 µm 282,276 2.82 100,098 1,111 71.10
TSMC .13 µm 747,667 5.0922 146,825 787 50.36
TSMC .18 µm 1,367,393 9.9792 137,024 591 37.82

 

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