DES3 Core — Intel Implementation Results

The DES3 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following tables provide sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Non Pipelined Area Optimized

Intel Device

LEs/

ALUTs
Memory
I/Os

Fmax
(MHz)

Throughput
(Mbps)

Quartus

Cyclone-II
EP2C20-6

1062 - 326 87 116 7.2

Cyclone-III
EP3C4-6

1062 - 326 118 157 7.2

Stratix-II
EP2S15-3

517 - 326 169 225 7.2

Stratix-III
EP3SL50-2

516 - 326 243 324 7.2

Non Pipelined Speed Optimized

Intel Device

LEs/

ALUTs
Memory
I/Os

Fmax
(MHz)

Throughput
(Mbps)

Quartus

Cyclone-II
EP2C20-6

1623 - 326 130 173 7.2

Cyclone-III
EP3C4-6

1624 - 326 149 198 7.2

Stratix-II
EP2S15-3

711 - 326 205 273 7.2

Stratix-III
EP3SL50-2

709 - 326 273 364 7.2

Pipelined Speed Optimized

Intel Device

LEs/

ALUTs
Memory
I/Os

Fmax
(MHz)

Throughput
(Gbps)

Quartus

Cyclone-II
EP2C20-6

13871 - 326 142 9.08 7.2

Cyclone-III
EP3C4-6

13735 - 326 204 13.05 7.2

Stratix-II
EP2S15-3

5397 - 326 332 21.24 7.2

Stratix-III
EP3SL50-2

5358 - 326 363 23.32 7.2

 

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