Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • FIPS 46-3 Standard Compliant
  • Encryption/Decryption performed in 16 cycles
    (ECB mode)
  • 56 bits of security
  • For use in FPGA or ASIC designs
  • Verilog IP Core

Non Pipelined version

  • Small gate count

Pipelined version

  • Pipelined for maximum performance
  • Encryption/Decryption performed in 1 cycle
    (ECB mode) after an initial latency of 16 cycles

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

White Paper
AES Encryption and CAST’s AES IP Cores (PDF)

DES Data Encryption Standard Core

The DES core implements the Data Encryption Standard (DES) documented in the U.S. Government publication FIPS 46-3.

DES Symbol

The DES core is a block cipher, working on 64 bits of data at a time.  The DES core uses a single 64 bit key of which only 56 bits are used. Encoding and decoding operations are performed in 16 clocks per block, in Electronic Codebook (ECB) mode.

The DES core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs.  The DES IP Core is delivered as Verilog RTL Source code.

This DES Core non-pipelined version is implemented to minimize the gate count and FPGA resources. After an initial latency of 16 cycles, it can output encryption/decryption at every cycle. The design does not use any memories such as SRAM. 

The DES core pipelined version is implemented to maximize performance by pipelining the DES transformation algorithm.  The design does not use any memories such as SRAM. 

See representative implementation results (each in a new pop-up window):

ASIC numbersAltera numbersXilinx numbers

Applications

The DES core can be utilized for a variety of encryption applications including:

Example of DES Encrypted and Decrypted Data

The following example data may be used when testing the DES encryption and decryption operations.

Key = 0x0123456789abcdef 

PLAINTEXT0 = 0x4e6f772069732074
PLAINTEXT1 = 0x68652074696d6520
PLAINTEXT2 = 0x666f7220616c6c20

CIPHERTEXT0 = 0x3fa40e8a984d4815
CIPHERTEXT1 = 0x6a271787ab8883f9
CIPHERTEXT2 = 0x893d51ec4b563b53

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

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