- FIPS 46-3 Standard Compliant
- Encryption/Decryption performed in 16 cycles
- 56 bits of security
- For use in FPGA or ASIC designs
- Verilog IP Core
Non Pipelined version
- Small gate count
- Pipelined for maximum performance
- Encryption/Decryption performed in 1 cycle
(ECB mode) after an initial latency of 16 cycles
Security IP Core DES Data Encryption Standard Core
The DES core implements the Data Encryption Standard (DES) documented in the U.S. Government publication FIPS 46-3.
The DES core is a block cipher, working on 64 bits of data at a time. The DES core uses a single 64 bit key of which only 56 bits are used. Encoding and decoding operations are performed in 16 clocks per block, in Electronic Codebook (ECB) mode.
The DES core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs. The DES IP Core is delivered as Verilog RTL Source code.
This DES Core non-pipelined version is implemented to minimize the gate count and FPGA resources. After an initial latency of 16 cycles, it can output encryption/decryption at every cycle. The design does not use any memories such as SRAM.
The DES core pipelined version is implemented to maximize performance by pipelining the DES transformation algorithm. The design does not use any memories such as SRAM.
See representative implementation results (each in a new pop-up window):
The DES core can be utilized for a variety of encryption applications including:
- Secure File/Data transfer
- Electronic Funds Transfer
- Encrypted Storage Data
- Secure communications
The following example data may be used when testing the DES encryption
and decryption operations.
Key = 0x0123456789abcdef
PLAINTEXT0 = 0x4e6f772069732074
PLAINTEXT1 = 0x68652074696d6520
PLAINTEXT2 = 0x666f7220616c6c20
CIPHERTEXT0 = 0x3fa40e8a984d4815
CIPHERTEXT1 = 0x6a271787ab8883f9
CIPHERTEXT2 = 0x893d51ec4b563b53
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive simulation and rigorous code coverage measurements.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
- Sophisticated self-checking Testbench
- Simulation script, vectors, and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation