DES Core — XILINX FPGA Results

The DES can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following tables provide sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Non Pipelined Optimized for Speed

Xilinx Device

Slices

BRAM
I/Os

Fmax
(MHz)

Throughput
(Mbps)

ISE
Spartan-3E
3S1200E-5
558 - 190 124 496 12.2i
Spartan-6
6SLX25-3
218 - 190 156 624 12.2i
Virtex-4
4VLX15-12
545 - 190 121 484 9.2.04i
Virtex-5
 5VLX30-3
192 - 190 325 1300 12.2i
Virtex-6
6VLX130T-3
217 - 190 423 1692 12.2i

Pipelined Optimized for Speed

Xilinx Device

Slices

BRAM
I/Os

Fmax
(MHz)

Throughput
(Gbps)

ISE
Spartan-3E
3S1200E-5
2368 - 190 134 8.57 12.2i
Spartan-6
6SLX25-3
719 - 190 95 6.08 12.2i
Virtex-4
4VLX15-12
2483 - 190 230 14.72 9.2.04i
Virtex-5
 5VLX30-3
816 - 190 320 20.48 12.2i
Virtex-6
 6VLX130T-3
638 - 190 332 21.24 12.2i

 

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