DES ASIC Implementation Results

The DES can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following tables provide sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Non Piplined Optimized for Area

ASIC Technology

Cell
Area

NAND2 Area Used

Approx. Area
(gate equiv.)
Frequency
(MHz)

Throughput (Mbps)

TSMC .09 µm 7,297 2.82 2,588 334 1336
TSMC .13 µm 14,793 5.0922 2,905 232 928
TSMC .18 µm 29,958 9.9792 3,002 151 604

Non Pipelined Optimized for Speed

ASIC Technology

Cell
Area

NAND2 Area Used

Approx. Area
(gate equiv.)
Frequency
(MHz)

Throughput (Gbps)

TSMC .09 µm 8,411 2.82 2,983 625 2.50
TSMC .13 µm 20,525 5.0922 4,031 555 2.22
TSMC .18 µm 41,626 9.9792 4,171 416 1.66

Pipelined Optimized for Speed

ASIC Technology

Cell
Area

NAND2 Area Used

Approx. Area
(gate equiv.)
Frequency
(MHz)

Throughput (Gbps)

TSMC .09 µm 106,596 2.82 37,800 1,190 76.16
TSMC .13 µm 256,088 5.0922 50,290 813 52.03
TSMC .18 µm 502,010 9.9792 50,305 633 40.51

 

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