DES Core — Intel Implementation Results

The DES can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following tables provide sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Non Pipelined Area Optimized

Intel Device

LEs/

ALUTs
Memory
I/Os

Fmax
(MHz)

Throughput
(Mbps)

Quartus
Cyclone-II
EP2C20-6
934 - 198 109 436 7.2
Cyclone-III
EP3C4-6
934 - 198 117 468 7.2
Stratix-II
EP2S15-3
450 - 198 188 752 7.2

Stratix-III
EP3SL50-2

450 - 198 266 1064 7.2

 

Non Pipelined Speed Optimized

Intel Device

LEs/

ALUTs
Memory
I/Os

Fmax
(MHz)

Throughput
(Mbps)

Quartus
Cyclone-II
EP2C20-6
1493 - 198 140 560 7.2
Cyclone-III
EP3C4-6
1493 - 198 157 628 7.2
Stratix-II
EP2S15-3
642 - 198 250 1000 7.2

Stratix-III
EP3SL50-2

641 - 198 353 1412 7.2

Pipelined Speed Optimized

Intel Device

LEs/

ALUTs
Memory
I/Os

Fmax
(MHz)

Throughput
(Gbps)

Quartus
Cyclone-II
EP2C20-6
4451 - 198 224 14.33 7.2
Cyclone-III
EP3C4-6
4451 - 198 249 15.93 7.2
Stratix-II
EP2S15-3
1826 - 198 346 22.14 7.2

Stratix-III
EP3SL50-2

1810 - 198 407 26.04 7.2

 

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